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93LC46-I/MS PDF预览

93LC46-I/MS

更新时间: 2024-02-17 13:02:35
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
页数 文件大小 规格书
20页 510K
描述
64 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8, PLASTIC, MSOP-8

93LC46-I/MS 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:MSOP
包装说明:PLASTIC, MSOP-8针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.51风险等级:5.42
备用内存宽度:8最大时钟频率 (fCLK):2 MHz
JESD-30 代码:S-PDSO-G8JESD-609代码:e3
长度:3 mm内存密度:1024 bit
内存集成电路类型:EEPROM内存宽度:16
湿度敏感等级:1功能数量:1
端子数量:8字数:64 words
字数代码:64工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:64X16封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:SQUARE
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH并行/串行:SERIAL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.18 mm串行总线类型:MICROWIRE
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2.5 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:3 mm
Base Number Matches:1

93LC46-I/MS 数据手册

 浏览型号93LC46-I/MS的Datasheet PDF文件第5页浏览型号93LC46-I/MS的Datasheet PDF文件第6页浏览型号93LC46-I/MS的Datasheet PDF文件第7页浏览型号93LC46-I/MS的Datasheet PDF文件第9页浏览型号93LC46-I/MS的Datasheet PDF文件第10页浏览型号93LC46-I/MS的Datasheet PDF文件第11页 
93XX46, 93XX46A/B  
2.6  
ERASE/WRITE DISABLE AND ENABLE (EWDS/EWEN)  
The 93XX46, 93XX46A/B powers up in the ERASE/  
WRITE Disable (EWDS) state. All programming modes  
must be preceded by an ERASE/WRITE Enable  
(EWEN) instruction. Once the EWEN instruction is  
executed, programming remains enabled until an EWDS  
instruction is executed or Vcc is removed from the  
device. To protect against accidental data disturbance,  
the EWDSinstruction can be used to disable all ERASE/  
WRITE functions and should follow all programming  
operations. Execution of a READinstruction is indepen-  
dent of both the EWENand EWDSinstructions.  
FIGURE 2-5: EWDS TIMING  
TCSL  
CS  
CLK  
•••  
1
0
0
0
0
X
X
DI  
FIGURE 2-6: EWEN TIMING  
TCSL  
CS  
CLK  
•••  
1
0
0
1
1
X
X
DI  
2.7  
READ  
The READ instruction outputs the serial data of the  
addressed memory location on the DO pin. A dummy  
zero bit precedes the 8-bit (If ORG pin is low or A-Ver-  
sion devices) or 16-bit (If ORG pin is high or B-version  
devices) output string. The output data bits will toggle  
on the rising edge of the CLK and are stable after the  
specified time delay (TPD). Sequential read is possible  
when CS is held high. The memory data will automati-  
cally cycle to the next register and output sequentially.  
FIGURE 2-7: READ TIMING  
CS  
CLK  
DI  
An  
•••  
A0  
1
1
0
HIGH-Z  
DO  
0
Dx  
D0  
Dx  
D0  
Dx  
D0  
•••  
•••  
•••  
DS21749A-page 8  
2002 Microchip Technology Inc.  

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