Datasheet > 存储 > EEPROM> 93AA46AT-I/MSGX

93AA46AT-I/MSGX

更新时间： 2024-02-04 13:51:22

品牌	Logo	应用领域
美国微芯 - MICROCHIP		可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
12页	98K
描述
128X8 MICROWIRE BUS SERIAL EEPROM, PDSO8

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

93AA46AT-I/MSGX 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Not Recommended	零件包装代码：	SOIC
包装说明：	SOP, SOP8,.25	针数：	8
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.51	风险等级：	5.42
Is Samacsys：	N	其他特性：	100K ERASE/WRITE CYCLES MIN; DATA RETENTION > 40 YEARS
备用内存宽度：	8	最大时钟频率 (fCLK)：	2 MHz
数据保留时间-最小值：	200	耐久性：	1000000 Write/Erase Cycles
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e3
长度：	4.9 mm	内存密度：	1024 bit
内存集成电路类型：	EEPROM	内存宽度：	16
湿度敏感等级：	1	功能数量：	1
端子数量：	8	字数：	64 words
字数代码：	64	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	64X16	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP8,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	并行/串行：	SERIAL
峰值回流温度（摄氏度）：	260	电源：	2/5 V
认证状态：	Not Qualified	筛选级别：	TS 16949
座面最大高度：	1.75 mm	串行总线类型：	MICROWIRE
最大待机电流：	0.00003 A	子类别：	EEPROMs
最大压摆率：	0.001 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	1.8 V	标称供电电压 (Vsup)：	3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	40
宽度：	3.91 mm	最长写入周期时间 (tWC)：	10 ms
写保护：	SOFTWARE	Base Number Matches：	1

93AA46AT-I/MSGX 数据手册

93AA46/56/66

2.4

READ

2.0

FUNCTIONAL DESCRIPTION

When the ORG pin is connected to VCC, the (x16) orga-

nization is selected. When it is connected to ground,

The READ instruction outputs the serial data of the

addressed memory location on the DO pin. A dummy

zero bit precedes the 16 bit (x16 organization) or 8 bit

(x8 organization) output string. The output data bits will

toggle on the rising edge of the CLK and are stable after

the speciﬁed time delay (TPD). Sequential read is pos-

sible when CS is held high. The memory data will auto-

matically cycle to the next register and output

sequentially.

the (x8) organization is selected.

Instructions,

addresses and write data are clocked into the DI pin on

the rising edge of the clock (CLK). The DO pin is nor-

mally held in a high-Z state except when reading data

from the device, or when checking the READY/BUSY

status during a programming operation. The ready/

busy status can be veriﬁed during an Erase/Write oper-

ation by polling the DO pin; DO low indicates that pro-

gramming is still in progress, while DO high indicates

the device is ready. The DO will enter the high-Z state

on the falling edge of the CS.

2.5

Erase/Write Enable and Disable

(EWEN,EWDS)

The 93AA46/56/66 power up in the Erase/Write Disable

(EWDS) state. All programming modes must be pre-

ceded by an Erase/Write Enable (EWEN) instruction.

Once the EWEN instruction is executed, programming

remains enabled until an EWDS instruction is executed

or VCC is removed from the device. To protect against

accidental data disturb, the EWDS instruction can be

used to disable all Erase/Write functions and should fol-

low all programming operations. Execution of a READ

instruction is independent of both the EWEN and

EWDS instructions.

2.1

START Condition

The START bit is detected by the device if CS and DI

are both HIGH with respect to the positive edge of CLK

for the ﬁrst time.

Before a START condition is detected, CS, CLK, and DI

may change in any combination (except to that of a

START condition), without resulting in any device oper-

ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,

and WRAL). As soon as CS is HIGH, the device is no

longer in the standby mode.

2.6

ERASE

An instruction following a START condition will only be

executed if the required amount of opcode, address

and data bits for any particular instruction is clocked in.

The ERASE instruction forces all data bits of the spec-

iﬁed address to the logical “1” state. CS is brought low

following the loading of the last address bit. This falling

edge of the CS pin initiates the self-timed programming

cycle.

After execution of an instruction (i.e., clock in or out of

the last required address or data bit) CLK and DI

become don't care bits until a new start condition is

detected.

The DO pin indicates the READY/BUSY status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL). DO at logical “0” indicates that program-

ming is still in progress. DO at logical “1” indicates that

the register at the speciﬁed address has been erased

and the device is ready for another instruction.

2.2

DI/DO

It is possible to connect the Data In and Data Out pins

together. However, with this conﬁguration it is possible

for a “bus conﬂict” to occur during the “dummy zero” that

precedes the READ operation, if A0 is a logic HIGH

level. Under such a condition the voltage level seen at

Data Out is undeﬁned and will depend upon the relative

impedances of Data Out and the signal source driving

A0. The higher the current sourcing capability of A0,

the higher the voltage at the Data Out pin.

The ERASE cycle takes 4 ms per word typical.

2.7

WRITE

The WRITE instruction is followed by 16 bits (or by 8

bits) of data which are written into the speciﬁed

address. After the last data bit is put on the DI pin, CS

must be brought low before the next rising edge of the

CLK clock. This falling edge of CS initiates the self-

timed auto-erase and programming cycle.

2.3

Data Protection

During power-up, all programming modes of operation

are inhibited until VCC has reached a level greater than

1.4V. During power-down, the source data protection

circuitry acts to inhibit all programming modes when

VCC has fallen below 1.4V at nominal conditions.

The DO pin indicates the READY/BUSY status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL) and before the entire write cycle is complete.

DO at logical “0” indicates that programming is still in

progress. DO at logical “1” indicates that the register at

the speciﬁed address has been written with the data

speciﬁed and the device is ready for another instruc-

tion.

The EWEN and EWDS commands give additional pro-

tection against accidentally programming during nor-

mal operation.

After power-up, the device is automatically in the

EWDS mode. Therefore, an EWEN instruction must be

performed before any ERASE or WRITE instruction can

be executed.

The WRITE cycle takes 4 ms per word typical.

DS20067G-page 4

1996 Microchip Technology Inc.

1 2 345 6 7...12

中文翻译

下载PDF

与93AA46AT-I/MSGX相关器件

型号	品牌	获取价格	描述	数据表
93AA46A-TI/MSX	MICROCHIP	获取价格	128 X 8 MICROWIRE BUS SERIAL EEPROM, PDSO8, LEAD FREE, PLASTIC, MO-187, MSOP-8
93AA46AT-I/MSX	MICROCHIP	获取价格	128 X 8 MICROWIRE BUS SERIAL EEPROM, PDSO8, ROHS COMPLIANT, PLASTIC, MSOP-8
93AA46AT-I/OT	MICROCHIP	获取价格	1K Microwire Compatible Serial EEPROM
93AA46A-TI/OTG	MICROCHIP	获取价格	128 X 8 MICROWIRE BUS SERIAL EEPROM, PDSO6, LEAD FREE, PLASTIC, SC-74A, SOT-23, 6 PIN
93AA46AT-I/OTG	MICROCHIP	获取价格	1K Microwire Compatible Serial EEPROM
93AA46A-TI/OTGX	MICROCHIP	获取价格	128 X 8 MICROWIRE BUS SERIAL EEPROM, PDSO6, LEAD FREE, PLASTIC, SC-74A, SOT-23, 6 PIN
93AA46AT-I/OTGX	MICROCHIP	获取价格	EEPROM, 128X8, Serial, CMOS, PDSO6
93AA46A-TI/OTX	MICROCHIP	获取价格	128 X 8 MICROWIRE BUS SERIAL EEPROM, PDSO6, LEAD FREE, PLASTIC, SC-74A, SOT-23, 6 PIN
93AA46AT-I/P	MICROCHIP	获取价格	1K Microwire Compatible Serial EEPROM
93AA46AT-I/PG	MICROCHIP	获取价格	1K Microwire Compatible Serial EEPROM

与93AA46AT-I/MSGX相关文章

压敏电阻器在直流电路中的过压保护应用探讨
2024-06-07

2
电感耐压值及其与电感大小的关系
2024-06-07

5
CNY17F光耦合器：特性、应用、封装、引脚功能及替换型号解析
2024-06-07

4
DS1307资料解析：特性、引脚说明、替代推荐
2024-06-07

3

产品中心

服务支持

精选活动

关于我们

帮助中心

93AA46AT-I/MSGX

93AA46AT-I/MSGX 技术参数

93AA46AT-I/MSGX 数据手册

与93AA46AT-I/MSGX相关器件

与93AA46AT-I/MSGX相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

93AA46AT-I/MSGX

93AA46AT-I/MSGX 技术参数

93AA46AT-I/MSGX 数据手册

与93AA46AT-I/MSGX相关器件

与93AA46AT-I/MSGX相关文章

您还可以找

您在本页遇到什么问题？