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93776AF PDF预览

93776AF

更新时间: 2024-11-25 21:05:19
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
10页 112K
描述
PLL Based Clock Driver, 93776 Series, 6 True Output(s), 0 Inverted Output(s), PDSO28, 0.209 INCH, MO-150, SSOP-28

93776AF 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:0.209 INCH, MO-150, SSOP-28
针数:28Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.92
系列:93776输入调节:DIFFERENTIAL
JESD-30 代码:R-PDSO-G28JESD-609代码:e0
长度:10.2 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.012 A湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:28实输出次数:6
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP28,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):240
电源:2.5 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.1 ns座面最大高度:2 mm
子类别:Clock Drivers最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:5.3 mm
Base Number Matches:1

93776AF 数据手册

 浏览型号93776AF的Datasheet PDF文件第2页浏览型号93776AF的Datasheet PDF文件第3页浏览型号93776AF的Datasheet PDF文件第4页浏览型号93776AF的Datasheet PDF文件第5页浏览型号93776AF的Datasheet PDF文件第6页浏览型号93776AF的Datasheet PDF文件第7页 
ICS93776  
Integrated  
Circuit  
Systems,Inc.  
LowCostDDRPhaseLockLoopZeroDelayBuffer  
Recommended Application:  
DDR Zero Delay Clock Buffer  
PinConfiguration  
DDRC0  
DDRT0  
VDD  
DDRT1  
DDRC1  
GND  
SCLK  
CLK_INT  
CLK_INC  
1
2
3
4
5
6
7
8
9
28 GND  
27 DDRC5  
26 DDRT5  
25 DDRC4  
24 DDRT4  
23 VDD  
22 SDATA  
21 FB_INC  
20 FB_INT  
19 FB_OUTT  
18 FB_OUTC  
17 DDRT3  
16 DDRC3  
15 GND  
ProductDescription/Features:  
Low skew, low jitter PLL clock driver  
Max frequency supported = 266MHz (DDR 533)  
I2C for functional and output control  
Feedback pins for input to output synchronization  
Spread Spectrum tolerant inputs  
3.3V tolerant CLK_INT/C input  
VDDA 10  
GND 11  
VDD 12  
DDRT2 13  
DDRC2 14  
Switching Characteristics:  
CYCLE - CYCLE jitter: <100ps  
OUTPUT - OUTPUT skew: <100ps  
DUTY CYCLE: 48% - 52%  
28-Pin 209mil SSOP  
BlockDiagram  
Functionality  
INPUTS  
OUTPUTS  
PLL State  
AVDD CLK_INT CLKT CLKC FB_OUTT  
FB_OUTT  
FB_OUTC  
2.5V  
L
L
H
L
L
on  
on  
Coonnttrrooll  
SCLK  
(nom)  
DDRT0  
DDRC0  
Looggiicc  
SDATA  
2.5V  
(nom)  
H
H
H
DDRT1  
DDRC1  
DDRT2  
DDRC2  
FB_INC  
FB_INT  
DDRT3  
DDRC3  
PLLLL  
DDRT4  
DDRC4  
CLK_INT  
CLK_INC  
DDRT5  
DDRC5  
0793A—03/08/05  
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.  
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.  

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