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935154220112 PDF预览

935154220112

更新时间: 2024-11-21 18:21:31
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管外围集成电路
页数 文件大小 规格书
23页 147K
描述
SPECIALTY MICROPROCESSOR CIRCUIT, PDIP8, 0.300 INCH, PLASTIC, MO-001, SOT-97-1, DIP-8

935154220112 技术参数

生命周期:Obsolete包装说明:DIP,
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.63JESD-30 代码:R-PDIP-T8
长度:9.5 mm端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
座面最大高度:4.2 mm最大供电电压:12 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:NO技术:BIPOLAR
温度等级:INDUSTRIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUIT
Base Number Matches:1

935154220112 数据手册

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P82B715  
I2C-bus extender  
Rev. 08 — 9 November 2009  
Product data sheet  
1. General description  
The P82B715 is a bipolar IC intended for application in I2C-bus and derivative bus  
systems. While retaining all the operating modes and features of the I2C-bus it permits  
extension of the practical separation distance between components on the I2C-bus by  
buffering both the data (SDA) and the clock (SCL) lines.  
The I2C-bus capacitance limit of 400 pF restricts practical communication distances to a  
few meters. Using one P82B715 at each end of a long cable (connecting Lx/Ly to Lx/Ly)  
reduces that cable’s loading on the linked I2C-buses by a factor of 10 and allows the total  
system capacitance load (all devices, cable, connectors, and traces or wires connected to  
the I2C-bus) to be around 3000 pF while the loading on each I2C-bus on the Sx/Sy sides  
remains below 400 pF. Longer cables or low-cost, general-purpose wiring may be used to  
link I2C-bus based modules without degrading noise margins. Multiple P82B715s can be  
connected together, linking their Lx/Ly ports, in a star or multi-point architecture as long as  
the total capacitance of the system is less than about 3000 pF and each bus at an Sx/Sy  
connection is well below 400 pF. This configuration, with the master and/or slave devices  
attached to the Sx/Sy port of each P82B715, has full multi-master communication  
capability. The P82B715 alone does not support voltage level translation, but it can be  
simply implemented using low cost transistors when required. There is no restriction on  
interconnecting the Sx/Sy I/Os, and, because the device output levels are always held  
within 100 mV of input drive levels, P82B715 is compatible with bus buffers that use  
voltage level offsets, e.g., PCA9511A, PCA9517, Sx/Sy side of P82B96.  
The lower VOL level and ability to operate with any master, slave or bus buffer is the  
primary advantage of the using the P82B715 for long distance buses at the disadvantage  
of not isolating bus capacitance like the P82B96 or PCA9600 are able to do. The primary  
disadvantage of the P82B96 and PCA9600 is that the static level offset needed to isolate  
bus capacitance does not allow these devices to operate with other bus buffers with  
special offset levels or with master/slaves that require a VIL lower than 0.8 V with noise  
margin. A proven quick design-in point-to-point/multi-point circuit (Figure 9) is included in  
Section 8.2 to allow rapid use of the P82B715 along with comparison waveforms so that  
the designer can clearly see the trade-offs between the P82B715 and the  
P82B96/PCA9600 and choose the type of device that is best for their application.  
2. Features  
I Dual, bidirectional, unity voltage gain buffer with no external directional control  
required  
I Compatible with I2C-bus and its derivatives SMBus, PMBus, DDC, etc.  
I Logic signal levels may include (but not exceed) both supply and ground  
I Logic signal input voltage levels are output without change and are independent of VCC  
I ×10 impedance transformation, but does not change logic voltage levels  

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