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935032890623 PDF预览

935032890623

更新时间: 2024-11-21 19:49:15
品牌 Logo 应用领域
恩智浦 - NXP 信息通信管理光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
15页 306K
描述
ABT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20, 7.50 MM WIDTH, PLASTIC, MS-013, SOT163-1, SOP-20

935032890623 技术参数

生命周期:Obsolete包装说明:SOP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84其他特性:WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
系列:ABTJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:12.8 mm
逻辑集成电路类型:BUS TRANSCEIVER位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE传播延迟(tpd):4.6 ns
座面最大高度:2.65 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:7.5 mm
Base Number Matches:1

935032890623 数据手册

 浏览型号935032890623的Datasheet PDF文件第2页浏览型号935032890623的Datasheet PDF文件第3页浏览型号935032890623的Datasheet PDF文件第4页浏览型号935032890623的Datasheet PDF文件第5页浏览型号935032890623的Datasheet PDF文件第6页浏览型号935032890623的Datasheet PDF文件第7页 
74ABT623  
Octal transceiver with dual enable; non-inverting; 3-state  
Rev. 03 — 22 October 2009  
Product data sheet  
1. General description  
The 74ABT623 high performance BiCMOS device combines low static and dynamic  
power dissipation with high speed and high output drive.  
The 74ABT623 is an octal transceiver featuring non-inverting 3-state bus compatible  
outputs in both send and receive directions. This octal bus transceiver is designed for  
asynchronous two-way communication between data buses.  
The control function implementation allows maximum flexibility in timing. This device  
allows data transmission from the A bus to the B bus or from the B bus to the A bus,  
depending upon the logic levels at the enable inputs (pins OEAB and OEBA). The enable  
inputs can be used to disable the device so that the buses are effectively isolated. The  
dual enable function configuration gives this transceiver the capability to store data by  
simultaneous enabling of pins OEAB and OEBA. Each output reinforces its input in this  
transceiver configuration. Thus, when both control inputs are enabled and all other data  
sources to the two sets of the bus lines are at high-impedance OFF-state, both sets of the  
bus lines will remain at their last states. The 8-bit codes appearing on the two sets of  
buses will be identical.  
2. Features  
I Octal bidirectional bus interface  
I 3-state buffers  
I Power-up 3-state  
I Output capability: +64 mA and 32 mA  
I data inputs are disabled during 3-state mode  
I Latch-up protection exceeds 500 mA per JESD78B class II level A  
I ESD protection:  
N HBM JESD22-A114F exceeds 2000 V  
N MM JESD22-A115-A exceeds 200 V  

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