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9212AF-13LF-IN0

更新时间： 2024-11-29 20:06:43
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
7页 161K
描述
Processor Specific Clock Generator, 533.3MHz, PDSO24, 0.150 INCH, GREEN, SSOP-24

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中文翻译

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9212AF-13LF-IN0 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：0.150 INCH, GREEN, SSOP-24针数：24
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.46
JESD-30 代码：R-PDSO-G24JESD-609代码：e3
长度：8.6868 mm端子数量：24
最高工作温度：70 °C最低工作温度：
最大输出时钟频率：533.3 MHz封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：260
主时钟/晶体标称频率：66.66 MHz认证状态：Not Qualified
座面最大高度：1.7272 mm最大供电电压：3.465 V
最小供电电压：3.135 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：3.937 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：1

9212AF-13LF-IN0 数据手册

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ICS9212-13  
Integrated  
Circuit  
Systems, Inc.  
Direct Rambus™ Clock Generator  
General Description  
Features  
•
•
Compatible with all Direct Rambus™ based IC s  
Up to 600 MHz differential clock source for direct  
Rambus™ memory system  
Cycle to cycle jitter is less than 40ps  
3.3 + 5% supply  
Synchronization flexibility: Supports Systems that  
need clock domains of Rambus channel to  
synchronize with system or processor clock, or  
systems that do not require synchronization of the  
Rambus clock to another system clock  
The ICS9212-13 is a High-speed clock generator providing  
up to 600 MHz differential clock source for direct Rambus™  
memory system. It includes DDLL (Distributed Delay  
locked loop) and phase detection mechanism to  
synchronize the direct Rambus™ channel clock to an  
external system clock. ICS9212-13 provides a solution for  
a broad range of Direct Rambus memory applications.The  
device works in conjunction with the ICS9250-09.  
•
•
•
The ICS9212-13 power management support system  
turns “off” the Rambus™ channel clock to minimize power  
consumption for mobile and other power–sensitive  
applications. In “clock off” mode the device remains “on”  
while the output is disabled, allowing fast transitions  
between clock-off and clock–on states. In “power down”  
mode it completely powers down for minimum power  
dissipation.  
•
•
Excellent power management support  
REFCLK input is from the ICS9250-09.  
The ICS9212-13meetstherequirementsforinputfrequency  
tracking when the input frequency clock is using Spread  
Spectrum clocking and also the optimum bandwidth is  
maintained while attenuating the jitter of the reference  
signal.  
Block Diagram  
BUSCLK_STOP#  
Pin Configuration  
VDDREF  
REFCLK  
VDD1  
1
2
3
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
FS0  
FS1  
VDD-OUT  
GND-OUT  
BUSCLKT  
N/C  
PD#  
FS(0:1)  
Test MUX  
GND1  
4
Bypass MUX  
GND3  
5
GND  
Bypclk  
PCLK/M  
SYNCLK/N  
GND2  
6
7
8
9
10  
11  
12  
PLLclk  
PLL  
BUSCLKC  
GND-OUT  
VDD-OUT  
MULTI0  
MULTI1  
FS2  
Refclk  
B
A
BUSCLKT  
BUSCLKC  
Phase  
Aligner  
VDD2  
VDDPD  
BUSCLK_STOP#  
PD#  
PAclk  
GND  
Phase  
Detector  
Multi(0:1)  
2
Pclk/M  
Synclk/N  
24-Pin 150 Mil SSOP  
0272F—08/08/07  
1234567

中文翻译

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