DG408MIL, DG409MIL
Vishay Siliconix
8-Ch/Dual 4-Ch High-Performance CMOS Analog Multiplexers
DESCRIPTION
FEATURES
• Low on-resistance - RDS(on): 100
• Low charge injection - Q: 20 pC
• Fast transition time - tTRANS: 160 ns
• Low power - ISUPPLY: 10 μA
• Single supply capability
• 44 V supply max. rating
The DG408 is an 8 channel single-ended analog multiplexer
designed to connect one of eight inputs to a common output
as determined by a 3-bit binary address (A0, A1, A2). The
DG409 is a dual 4 channel differential analog multiplexer
designed to connect one of four differential inputs to a
common dual output as determined by its 2-bit binary
address (A0, A1). Break-before-make switching action
protects against momentary crosstalk between adjacent
channels.
• TTL compatible logic
BENEFITS
• Reduced switching errors
• Reduced glitching
• Improved data throughput
• Reduced power consumption
• Increased ruggedness
• Wide supply ranges ( 5 V to 20 V)
An on channel conducts current equally well in both
directions. In the off state each channel blocks voltages up
to the power supply rails. An enable (EN) function allows the
user to reset the multiplexer/demultiplexer to all switches off
for stacking several devices. All control inputs, address (Ax)
and enable (EN) are TTL compatible over the full specified
operating temperature range.
Applications for the DG408, DG409 include high speed data
acquisition, audio signal switching and routing, ATE
systems, and avionics. High performance and low power
dissipation make them ideal for battery operated and
remote instrumentation applications.
APPLICATIONS
• Data acquisition systems
• Audio signal routing
• ATE systems
Designed in the 44 V silicon-gate CMOS process, the
absolute maximum voltage rating is extended to 44 V.
Additionally, single supply operation is also allowed. An
epitaxial layer prevents latchup.
• Battery powered systems
• High rel systems
• Single supply systems
• Medical instrumentation
For additional information please see Technical Article
TA201.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
CerDIP
Top View
CerDIP
Top View
DG409
DG408
A
A
A
A
A
1
0
1
2
0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
EN
V-
EN
V-
GND
V+
Decoders/Drivers
Decoders/Drivers
GND
V+
S
S
S
S
S
S
S
S
1
2
1a
2a
3a
1b
2b
3b
S
S
S
S
S
S
5
6
7
3
4
S
4a
4b
D
S
D
D
b
8
a
Document Number: 67952
S11-1003-Rev. A, 23-May-11
www.vishay.com
1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000