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91309YGLFT PDF预览

91309YGLFT

更新时间: 2024-02-05 17:26:04
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
10页 108K
描述
PLL Based Clock Driver, 91309 Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, LEAD FREE, TSSSOP-8

91309YGLFT 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:End Of Life零件包装代码:SOIC
包装说明:LEAD FREE, TSSSOP-8针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.68Is Samacsys:N
系列:91309输入调节:STANDARD
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:5 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:8实输出次数:4
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.7 ns
座面最大高度:1.2 mm最大供电电压 (Vsup):3.4 V
最小供电电压 (Vsup):3.2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
最小 fmax:133 MHzBase Number Matches:1

91309YGLFT 数据手册

 浏览型号91309YGLFT的Datasheet PDF文件第1页浏览型号91309YGLFT的Datasheet PDF文件第2页浏览型号91309YGLFT的Datasheet PDF文件第3页浏览型号91309YGLFT的Datasheet PDF文件第5页浏览型号91309YGLFT的Datasheet PDF文件第6页浏览型号91309YGLFT的Datasheet PDF文件第7页 
ICS91309  
Electrical Characteristics - Outputs  
TA = 0 - 70°C; VDD = 3.3 V +/-10%; CL = 30 pF (unless otherwise specified)  
PARAMETER  
Output High Voltage  
Output Low Voltage  
Rise Time1  
SYMBOL  
VOH  
CONDITIONS  
MIN  
2.4  
TYP  
MAX  
UNITS  
V
V
ns  
IOH = -12 mA  
IOL = 12 mA  
VOL  
tr  
tf  
TLOCK  
f1  
f1  
Dt1  
Dt2  
0.4  
1.5  
1.5  
1
100  
133  
60  
Measure between 0.8 V and 2.0 V  
Measure between 2.0 V and 0.8 V  
Stable VDD, valid clock on REF  
CL = 30 pF  
1.2  
1.2  
Fall Time1  
ns  
PLL Lock Time1  
mS  
MHz  
MHz  
%
%
ps  
ps  
ps  
ps  
ps  
10  
10  
40  
45  
Output Frequency  
CL = 10 pF  
Measured at 1.4 V, Fout = 66.7 MHz  
Measured at VDD/2, Fout < 50.0 MHz  
50  
50  
Duty Cycle1  
55  
Jitter, Cycle-to-cycle1  
Jitter, Absolute1  
tjcyc-cyc  
Tjabs  
Tj1s  
Tsk  
Tsk  
Tdsk-Tdsk  
Dr1  
Measured at 66.7 MHz, loaded outputs  
10,000 cycles, CL = 30 pF  
10,000 cycles, CL = 30 pF  
Measured at 1.4 V  
Measured at 1.4 V, within a group  
Measured at VDD/2,on CLKOUT pins  
Measured at 1.4 V  
125  
100  
30  
215  
100  
700  
700  
-100  
70  
14  
Jitter, 1-Sigma1  
Skew, Group-to-Group1  
Skew, Output-to-Output1  
Skew, Device-to-Device1  
Delay, Input-to-Output1  
ps  
ps  
Notes:  
1. Guaranteed by design and characterization, not 100% tested in production.  
0093H—12/09/08  
4

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