Datasheet > 91309YGT

91309YGT

更新时间： 2024-02-28 10:04:59

品牌	Logo	应用领域
艾迪悌 - IDT		驱动逻辑集成电路
页数	文件大小	规格书
11页	290K
描述
PLL Based Clock Driver

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技术参数
数据手册

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91309YGT 技术参数

生命周期：	Active	Reach Compliance Code：	compliant
风险等级：	5.68	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
Base Number Matches：	1

91309YGT 数据手册

ICS91309

High Performance Communication Buffer

General Description

Features

The ICS91309 is a high performance, low skew, low jitter

zero delay buffer. It uses a phase lock loop (PLL)

technologytoalign, inbothphaseandfrequency, theREF

input with the CLKOUT signal. It is designed to distribute

high speed clocks in communication systems operating

at speeds from 10 to 133 MHz.

•

Zero input - output delay

Frequency range 10 - 133 MHz (3.3V)

5V tolerant input REF

High loop filter bandwidth ideal for Spread Spectrum

applications.

•

Less than 125 ps cycle to cycle Jitter

Skew controlled outputs

Available in 16 pin, 150 mil SSOP, SOIC & 4.40mm

TSSOP packages

The ICS91309 provides synchronization between the

input and output. The synchronization is established via

CLKOUTfeedbacktotheinputofthePLL. Sincetheskew

between the input and output is less than +/- 350 pS, the

part acts as a zero delay buffer.

•

Skew:Group-to-Group:<215ps

Skew within Group: <100 ps

Commercial temperature range: 0°C to +70°C

ICS91309 hastwobanksoffouroutputscontrolledbytwo

address lines. Depending on the selected address line,

bankBorbothbankscanbeputinatri-statemode. Inthis

mode, the PLL is still running and only the output buffers

are put in a high impedance mode. The test mode shuts

off the PLL and connects the input directly to the output

buffers (see table below for functionality).

Pin Configuration

REF

CLKA1

CLKA2

VDD

CLKOUT

CLKA4

CLKA3

VDD

ICS91309 comes in a 16-pin 150 mil SOIC, SSOP or

4.40mm TSSOP package. In the absence of REF input,

thedevicewillenterapowerdownmode. Inthismode, the

PLL is turned off and the output buffers are pulled low.

Powerdownmodeprovidesthelowestpowerconsumption

for a standby condition.

GND

CLKB1

CLKB2

FS2

CLKB4

CLKB3

FS1

Block Diagram

16 pin SSOP, SOIC & TSSOP

Functionality

Ouput

Source Shutdown

PLL

FS2 FS1 CLKA(1:4) CLKB(1:4) CLKOUT

Tristate

Driven

PLL

Bypass

Mode

Tristate

Driven

PLL

Bypass

Mode

Driven

PLL

PLL Bypass

Mode

REF

PLL

Driven

0093H—12/09/08

12 3 4 5 6 7...11

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