Datasheet > 8V41N010NLGI8

8V41N010NLGI8

更新时间： 2022-02-26 12:30:22

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
26页	533K
描述
Clock Generator for Cavium Processors

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8V41N010NLGI8 数据手册

Clock Generator for Cavium Processors

8V41N010

DATA SHEET

General Description

Features

The 8V41N010 is a PLL-based clock generator specifically designed

for Cavium Networks Octeon II processors. This high performance

device is optimized to generate the processor core reference clock,

the PCI-Express, sRIO, XAUI, SerDes reference clocks and the

clocks for both the Gigabit Ethernet MAC and PHY. The output fre-

quencies are generated from a 25MHz external input source or an

external 25MHz parallel resonant crystal. The industrial temperature

range of the 8V41N010 supports telecommunication, networking,

and storage requirements.

• Eight selectable 100MHz and 156.25MHz clocks for PCI Express,

sRIO and GbE, HCSL interface levels

• One single-ended QF LVCMOS/LVTTL clock output at 50MHz

• Selectable external crystal or differential (single-ended)

input source

• Crystal oscillator interface designed for 25MHz, parallel

resonant crystal

• Differential CLK, nCLK input pair that can accept: LVPECL, LVDS,

LVHSTL, HCSL input levels

• Internal resistor bias on nCLK pin allows the user to drive CLK

input with external single-ended (LVCMOS/ LVTTL) input levels

• Full 3.3V supply mode

• -40°C to 85°C ambient operating temperature

• Lead-free (RoHS 6) packaging

Pin Assignment

54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37

QE0

nQE0

QE1

GND

nQE1

GND

OE_E

nQB0

QB0

V_{DDO_QB}

OE_A

GND

nQA1

QA1

8XXXXXX

FSEL_C1

GND

V_DDA

8V41N010

nQA0

QA0

FSEL_D1

V_DD

V_{DDO_QA}

GND

V_DD

nMR

V_DDO

GND

V_{DDO_QF}

10 11 12 13 14 15 16 17 18

NOTE: Exposed pad must always be connected to GND.

NOTE: Pin 1 is located at bottom left corner as shown.

72-pin, 10mm x 10mm VFQFN Package

8V41N010 REVISION 1 06/30/15

12 3 4 5 6 7...26

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