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8V44S269 PDF预览

8V44S269

更新时间: 2024-02-17 02:33:00
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
28页 598K
描述
FemtoClock Crystal-to-LVDS, LVCMOS 10-Output Clock Synthesizer

8V44S269 数据手册

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FemtoClock® Crystal-to-LVDS, LVCMOS  
10-Output Clock Synthesizer  
8V44S269  
Datasheet  
General Description  
Features  
The 8V44S269 is a ten LVDS/LVTTL output clock synthesizer  
designed for instrumentation and wireless applications. The device  
generates four copies of a 125MHz, two copies of a 100MHz  
differential LVDS clock and one 50MHz (LVCMOS) signal with  
excellent phase jitter performance. The PLL is optimized for a  
reference frequency of 25MHz. Both a crystal interface and a  
single-ended input are supported for the reference frequency. Three  
LVCMOS outputs duplicate the reference frequency and are  
provided for clock tree cascade purpose. Each of the four LVCMOS  
outputs can be supplied with either 3.3V, 2.5V or 1.8V, forming the  
respective LVCMOS output levels of 3.3V, 2.5V or 1.8V. The device  
uses IDT’s third generation FemtoClock® technology for an optimum  
of high clock frequency and low phase noise performance, combined  
with a low power consumption. The device supports a 3.3V voltage  
supply and is packaged in a small, lead-free (RoHS 6) 48-lead  
VFQFN package.  
Third generation FemtoClock® technology  
125MHz, 100MHz and 50MHz output clocks synthesized from a  
25MHz reference clock or fundamental mode crystal  
Six differential LVDS clock outputs  
QA[0:3] outputs (125MHz) are LVDS compatible  
QB[0:1] outputs (100MHz) are LVDS compatible  
Four single-ended LVCMOS-compatible reference clock outputs  
QC output (50MHz) is LVCMOS 3.3V, 2.5V or 1.8V compatible  
QREF[0:2] (25MHz) are LVCMOS 3.3V, 2.5V or 1.8V compatible  
Crystal interface designed for 25MHz XTAL  
RMS phase jitter @ 125MHz, using a 25MHz crystal  
(12kHz - 20MHz): 0.57 (typical)  
RMS phase jitter @ 100MHz, using a 25MHz crystal  
(12kHz - 20MHz): 0.58 (typical)  
LVCMOS interface levels for the control input  
I/O supply voltages for LVDS:  
Core/Output  
3.3V/2.5V  
I/O supply voltages for LVCMOS:  
Core/Output  
3.3V/3.3V  
3.3V/2.5V  
3.3V/1.8V  
Lead-free (RoHS 6) 48-lead VFQFN packaging  
-55°C to 105°C ambient operating temperature  
©2016 Integrated Device Technology, Inc.  
1
May 9, 2016  

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