Datasheet > 8V43FS92432PRGI8

8V43FS92432PRGI8

更新时间： 2024-01-17 06:05:14

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
27页	392K
描述
1360MHz Dual Output LVPECL Clock Synthesizer

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8V43FS92432PRGI8 数据手册

1360MHz Dual Output LVPECL

Clock Synthesizer

8V43FS92432

DATA SHEET

General Description

Features

The 8V43FS92432 is a 3.3V-compatible, PLL based clock

synthesizer targeted for high performance clock generation in

mid-range to high-performance telecom, networking, and computing

applications. With output frequencies from 21.25MHz to 1360MHz

and the support of two differential PECL output signals, the device

meets the needs of the most demanding clock applications.

• 21.25MHz to 1360MHz synthesized clock output signal

• Two differential, LVPECL-compatible high-frequency outputs

• Output frequency programmable through 2-wire I²C bus or

parallel interface

• On-chip crystal oscillator for reference frequency generation

• Alternative LVCMOS compatible reference clock input

• Synchronous clock stop functionality for both outputs

• LOCK indicator output (LVCMOS)

• LVCMOS compatible control inputs

• Fully integrated PLL

• 3.3-V power supply

• 48-lead LQFP

• 48-lead Pb-free package available

• SiGe Technology

• Ambient temperature range: –40°C to +85°C

The 8V43FS92432 is a programmable high-frequency clock source

(clock synthesizer). The internal PLL generates a high-frequency

output signal based on a low-frequency reference signal. The

frequency of the output signal is programmable and can be changed

on the fly for frequency margining purpose.

The internal crystal oscillator uses the external quartz crystal as the

basis of its frequency reference. Alternatively, a LVCMOS compatible

clock signal can be used as a PLL reference signal. The frequency of

the internal crystal oscillator is divided by a selectable divider and

then multiplied by the PLL. Its output is scaled by a divider that is

configured by either the I²C or parallel interfaces. The crystal

oscillator frequency f_XTAL,the PLL pre-divider P, the feedback-divider

M, and the PLL post-divider N determine the output frequency. The

feedback path of the PLL is internal.

Applications

The PLL post-divider N is configured through either the I²C or the

parallel interfaces, and can provide one of six division ratios (2, 4, 8,

16, 32, 64). This divider extends the performance of the part while

providing a 50% duty cycle. The high-frequency outputs, Q_Aand Q_B,

are differential and are capable of driving a pair of transmission lines

terminated 50 to V_CC– 2.0 V. The second high-frequency output,

Q_B, can be configured to run at either 1x or 1/2x of the clock

frequency or the first output (Q_A). The positive supply voltage for the

internal PLL is separated from the power supply for the core logic

and output drivers to minimize noise induced jitter.

• Programmable clock source for server, computing, and

telecommunication systems

• Frequency margining

• Oscillator replacement

The configuration logic has two sections: I²C and parallel. The

parallel interface uses the values at the M[9:0], NA[2:0], NB, and P

parallel inputs to configure the internal PLL dividers. The parallel

programming interface has priority over the serial I²C interface. The

serial interface is I²C compatible and provides read and write access

to the internal PLL configuration registers. The lock state of the PLL

is indicated by the LVCMOS-compatible LOCK output.

8V43FS92432 REVISION 1 10/28/15

12 3 4 5 6 7...27

中文翻译

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