Datasheet > 8T49N285-998NLGI

8T49N285-998NLGI

更新时间： 2024-01-14 01:22:34

品牌	Logo	应用领域
艾迪悌 - IDT		时钟外围集成电路晶体
页数	文件大小	规格书
67页	1336K
描述
PLL/Frequency Synthesis Circuit, PQCC56

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技术参数
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8T49N285-998NLGI 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	HVQCCN,	Reach Compliance Code：	compliant
风险等级：	5.77	其他特性：	IT ALSO OPERATES AT 3.3V NOMINAL SUPPLY
JESD-30 代码：	S-XQCC-N56	JESD-609代码：	e3
长度：	8 mm	端子数量：	56
最高工作温度：	85 °C	最低工作温度：	-40 °C
最大输出时钟频率：	1000 MHz	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
主时钟/晶体标称频率：	40 MHz	座面最大高度：	1 mm
最大供电电压：	2.625 V	最小供电电压：	2.375 V
标称供电电压：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	8 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC	Base Number Matches：	1

8T49N285-998NLGI 数据手册

FemtoClock^®NG Octal Universal

Frequency Translator

8T49N285

Datasheet

Description

Features

The 8T49N285 has a fractional-feedback PLL that can be used as a

jitter attenuator or frequency translator. It is equipped with six integer

and two fractional output dividers, allowing the generation of up to 8

different output frequencies, ranging from 8kHz to 1GHz. Three of

these frequencies are completely independent of each other and the

inputs. The other five are related frequencies. The eight outputs may

select among LVPECL, LVDS, HCSL or LVCMOS output levels.

• Supports SDH/SONET and Synchronous Ethernet clocks

including all FEC rate conversions

• <0.3ps RMS typical jitter (including spurs),12kHz to 20MHz

• Operating modes: locked to input signal, holdover and free-run

• Initial holdover accuracy of ±50ppb

• Accepts two LVPECL, LVDS, LVHSTL, HCSL or LVCMOS 

input clocks

This functionality makes it ideal to be used in any frequency

translation application, including 1G, 10G, 40G, and 100G

Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T

G.709 (2009) FEC rates. The device may also behave as a frequency

synthesizer.

• Accepts frequencies ranging from 8kHz up to 875MHz

• Auto and manual input clock selection with hitless switching

• Clock input monitoring, including support for gapped clocks

• Phase-Slope Limiting and Fully Hitless Switching options to

The 8T49N285 accepts up to two differential or single-ended input

clocks and a crystal input. The PLL can lock to either input clock, but

both input clocks must be related in frequency.

control output phase transients

• Operates from a 10MHz to 40MHz fundamental-mode crystal

• Generates 8 LVPECL/LVDS/HCSL or 16 LVCMOS output clocks

• Output frequencies ranging from 8kHz up to 1.0GHz (diff)

• Output frequencies ranging from 8kHz to 250MHz (LVCMOS)

The device supports hitless reference switching between input

clocks. The device monitors both input clocks for Loss of Signal

(LOS). It generates an alarm when an input clock failure is detected.

Automatic and manual hitless reference switching options are

supported. LOS behavior can be set to support gapped or un-gapped

clocks.

• Four General Purpose I/O pins with optional support for status &

control:

The 8T49N285 supports holdover with an initial accuracy of ±50ppB

from the point where the loss of all applicable input reference(s) has

been detected. It maintains a historical average operating point that

may be returned to in holdover at a limited phase slope.

• Four Output Enable control inputs may be mapped to any of the

eight outputs

• Lock, Holdover & Loss-of-Signal status outputs

• Open-drain Interrupt pin

The device places no constraints on input to output frequency

conversion, supporting all FEC rates, including the new revision of

ITU-T Recommendation G.709 (2009), most with 0ppm conversion

error.

• Nine programmable PLL loop bandwidth settings from 1.4Hz to

360Hz.

• Optional Fast Lock function

The PLL has a register-selectable loop bandwidth from 1.4Hz to

360Hz.

• Programmable output phase delays in steps as small as 16ps

• Register programmable through I²C or via external I²C EEPROM

• Bypass clock paths for system tests

Each output supports individual phase delay settings to allow

output-output alignment.

• Power supply modes

The device supports Output Enable inputs and Lock, Holdover and

LOS status outputs.

The device is programmable through an I²C interface. It also supports

I²C master capability to allow the register configuration to be read

from an external EEPROM.

V_CC/ V_CCA/ V_CCO

3.3V / 3.3V / 3.3V

3.3V / 3.3V / 2.5V

3.3V / 3.3V / 1.8V (LVCMOS)

2.5V / 2.5V / 3.3V

2.5V / 2.5V / 2.5V

2.5V / 2.5V / 1.8V (LVCMOS)

Typical Applications

• -40°C to 85°C ambient operating temperature

• Package: 56QFN, lead-free RoHs (6)

• OTN or SONET / SDH equipment Line cards (up to OC-192, and

supporting FEC ratios)

• OTN de-mapping (Gapped Clock and DCO mode)

• Gigabit and Terabit IP switches / routers including support of

Synchronous Ethernet

• SyncE (G.8262) applications

• Wireless base station baseband

• Data communications

• 100G Ethernet

January 31, 2018

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与8T49N285-998NLGI相关器件

型号	品牌	获取价格	描述	数据表
8T49N285-999NLGI	IDT	获取价格	PLL/Frequency Synthesis Circuit, PQCC56
8T49N285-999NLGI8	IDT	获取价格	VFQFPN-56, Reel
8T49N285A-000NLGI	IDT	获取价格	FemtoClock NG Octal Universal Frequency Translator
8T49N285A-000NLGI8	IDT	获取价格	FemtoClock NG Octal Universal Frequency Translator
8T49N285A-001NLGI	IDT	获取价格	FemtoClock NG Octal Universal Frequency Translator
8T49N285A-001NLGI8	IDT	获取价格	FemtoClock NG Octal Universal Frequency Translator
8T49N285A-002NLGI	IDT	获取价格	FemtoClock NG Octal Universal Frequency Translator
8T49N285A-002NLGI8	IDT	获取价格	FemtoClock NG Octal Universal Frequency Translator
8T49N285A-006NLGI	IDT	获取价格	FemtoClock NG Octal Universal Frequency Translator
8T49N285A-006NLGI8	IDT	获取价格	FemtoClock NG Octal Universal Frequency Translator

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