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8R512SEA0200C25 PDF预览

8R512SEA0200C25

更新时间： 2024-02-16 22:31:44
品牌 Logo 应用领域
WEDC 静态存储器内存集成电路
页数 文件大小 规格书
11页 316K
描述
SRAM Card, 64KX8, 250ns, CMOS, CARD-68

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8R512SEA0200C25 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：CARD-68Reach Compliance Code：unknown
风险等级：5.92最长访问时间：250 ns
JESD-30 代码：R-XUUC-N68内存密度：524288 bit
内存集成电路类型：SRAM CARD内存宽度：8
功能数量：1端子数量：68
字数：65536 words字数代码：64000
工作模式：ASYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：64KX8
封装主体材料：UNSPECIFIED封装代码：DIE
封装形状：RECTANGULAR封装形式：UNCASED CHIP
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：NO LEAD
端子位置：UPPER处于峰值回流温度下的最长时间：NOT SPECIFIED

8R512SEA0200C25 数据手册

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SEA01-SEA04  
White Electronic Designs  
CARD SIGNAL DESCRIPTION  
Symbol  
Type  
Name and Function  
A0 - A25  
INPUT  
ADDRESS INPUTS: A0 through A25 enable direct addressing of up to 64MB of memory on the card. Signal A0 is not  
used in word access mode. A25 is the most significant bit. (address pins used are based on card density,see pinout  
for highest used address pin)  
DQ0 – DQ7  
DQ8 – DQ15  
INPUT/OUTPUT  
INPUT  
DATA INPUT/OUTPUT: DQ0 THROUGH DQ15 constitute the bi-directional databus. DQ0 - DQ7 constitute the lower  
(even) byte and DQ8 - DQ15 the upper (odd) byte. Upper byte is Not Connected on this card.  
CE1#, CE2#  
CARD ENABLE 1 AND 2: CE1# enables even byte accesses, CE2# control signal in PCMCIA standard, to access  
high byte, - not used on this card  
OE#  
INPUT  
OUTPUT ENABLE: Active low signal enabling read data from the memory card.  
WRITE ENABLE: Active low signal gating write data to the memory card.  
READY/BUSY OUTPUT: Not used for SRAM cards  
WE#  
INPUT  
RDY/BSY #  
CD1#, CD2#  
OUTPUT  
OUTPUT  
CARD DETECT 1 and 2: Provide card insertion detection. These signals are connected to ground internally on the  
memory card. The host socket interface circuitry shall supply 10K-ohm or larger pull-up resistors on these signal pins.  
WP  
OUTPUT  
N.C.  
WRITE PROTECT: Follows hardware Write Protect Switch. When Switch is placed in on position, signal is pulled high  
(10K ohm). When switch is off signal is pulled low.  
VPP1, VPP2  
VCC  
PROGRAM/ERASE POWER SUPPLY: Not used for SRAM cards.  
CARD POW ER SUPPLY: 5.0V for all internal circuitry.  
GND  
GROUND: for all internal circuitry.  
REG #  
INPUT  
ATTRIBUTE MEMORY SELECT: only used with cards built with optional attribute memory.  
RESET: Not used for SRAM cards  
RST  
INPUT  
WAIT #  
BVD1, BVD2  
OUTPUT  
OUTPUT  
WAIT: This signal is pulled high internally for compatibility. No wait states are generated.  
BATTERY VOLTAGE DETECT: Provides status of Battery voltage.  
BVD2 = BVD1 = VOH (battery voltage is guaranteed to retain data)  
BVD2 = VOL, BVD1 = VOH (data is valid, battery recharge required)  
BVD2 = BVD1 = VOL (data may no longer be valid, battery requires extended recharge)  
VS1, VS2  
OUTPUT  
VOLTAGE SENSE: Notifies the host socket of the card’s VCC requirements. VS1 and VS2 are open to indicate a 5V,  
16 bit card has been inserted.  
RFU  
N.C.  
RESERVED FOR FUTURE USE  
NO INTERNAL CONNECTION TO CARD: pin may be driven or left floating  
FUNCTIONAL TRUTH TABLE  
READ function  
Function Mode  
Standby Mode  
Common Memory  
D15-D8  
Attribute Memory  
D15-D8  
CE2# CE1# OE# WE#  
REG#  
D7-D0  
High-Z  
REG#  
D7-D0  
High-Z  
X
X
H
L
X
L
X
H
X
H
High-Z  
X
L
High-Z  
Byte Access (8 bits)  
High-Z  
Data Out  
High-Z  
Data Out  
WRITE function  
Standby Mode  
X
X
H
L
X
H
X
L
X
H
X
X
X
X
L
X
X
X
Byte Access (8 bits)  
Data In  
Data In  
February 2007  
Rev. 4  
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com  
12345678...11

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