Datasheet > 8P73S674_16

8P73S674_16

更新时间： 2024-10-02 01:05:15

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
15页	281K
描述
1.8V LVPECL Clock Divider

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数据手册

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8P73S674_16 数据手册

1.8V LVPECL Clock Divider

8P73S674

DATA SHEET

General Description

Features

The 8P73S674 is a 1.8V LVPECL Clock Divider and Fanout Buffer.

The device has been designed for clock signal division and fanout in

wireless base station (radio and base band), high-end computing and

telecommunication equipment. The device is optimized to deliver

excellent phase noise performance. The 8P73S674 uses SiGe

technology for an optimum of high clock frequency and low phase

noise performance, combined with high power supply noise rejection.

The device offers the frequency division by ÷1, ÷2, ÷4 and ÷8. Four

low-skew 1.8V LVPECL outputs are available for and support clock

output frequencies up to 1GHz (÷1 frequency division). 1.8V LVPECL

• Clock signal division and distribution

• SiGe technology for high-frequency and fast signal rise/fall times

• Four low-skew LVPECL clock outputs

• Supports frequency division of ÷1, ÷2, ÷4 and ÷8

• Maximum Output frequency: 1GHz

• Output skew: 100ps (maximum)

• LVPECL output rise/fall time (20% - 80%): 220ps (maximum)

• 1.8V core and output supply mode

outputs are terminated 50 to GND. Outputs can be disabled to save

power consumption if not used. The device is packaged in a lead-free

(RoHS 6) 20-lead VFQFN package. The extended temperature range

supports wireless infrastructure, telecommunication and networking

end equipment requirements. The device is a member of the

high-performance clock family from IDT.

• Supports 1.8V I/O LVCMOS logic levels for all control pins

• -40°C to +85°C ambient operating temperature

• Lead-free (RoHS 6) 20-lead VFQFN packaging

Block Diagram

Pin Assignment

nQ0

nIN

÷N

nIN

nQ1

2x 50



nQ1

N[1:0]

8P73S674

nQ2

nOEA

nOEB

nQ3

VCC

20-pin, 2.15mm x 2.15mm, EPad, VFQFN Package

8P73S674 REVISION 1 12/17/14

12 3 4 5 6 7...15

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