Datasheet > 8P79818NLGI

8P79818NLGI

更新时间： 2024-10-02 01:08:15

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
34页	869K
描述
Programmable Low Additive Jitter 2:8 Buffer with Dividers and Universal Outputs

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8P79818NLGI 数据手册

Programmable Low Additive Jitter 2:8

8P79818

Datasheet

Buffer with Dividers and Universal Outputs

Description

Features

▪ Two differential inputs support LVPECL, LVDS, HCSL or LVCMOS

The device is intended to take 1 or 2 reference clocks, select

between them, using a pin or register selection and generate up to 8

outputs that may be the same as the reference frequency or

integer-divider versions of it.

reference clocks

— Accepts input frequencies ranging from 1PPS (1Hz) to

700MHz

▪ Select which of the two input clocks is to be used as the reference

The 8P79818 supports two output banks, each with its own divider

and power supply. All outputs in one bank would generate the same

output frequency, but each output can be individually controlled for

output type, output enable or even powered-off.

clock for which divider via pin or register selection

— Switchover will not generate any runt clock pulses on the

output

▪ Generates eight differential outputs

The device supports a serial port for configuration of the parameters

while in operation. The serial port can be selected to use the I²C or

SPI protocol. After power-up, all outputs will come up in LVDS mode

and may be programmed to other configurations over the serial port.

Outputs may be enabled or disabled under control of the OE input

pin.

or eight LVCMOS outputs, Bank A only

— Differential outputs selectable as LVPECL, LVDS, CML or

HCSL

— Differential outputs support frequencies from 1PPS to 700MHz

— LVCMOS outputs support frequencies from 1PPS to 200MHz

The device can operate over the -40°C to +85°C temperature range.

— LVCMOS outputs in the same pair may be inverted or in-phase

relative to one another

▪ Outputs arranged in 2 banks of 4 outputs each

— Each bank supports a separate power supply of 3.3V, 2.5V or

1.8V

— 1.5V output voltage is also supported for LVCMOS, Bank A

only

— One divider per output bank, supporting divide ratios of 2...511

or divider bypass

▪ Output enable control pin

— Output enable or disable will not cause any runt pulses

▪ Register programmable via I²C / SPI serial port

— Individual output enables, output type selection and output

power-down control bits supported

— Input mux selection control bit

▪ Core voltage supply of 3.3V, 2.5V or 1.8V

▪ -40°C to +85°C ambient operating temperature

▪ Lead-free (RoHS 6) packaging

December 19, 2016

12 3 4 5 6 7...34

中文翻译

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