89HPES8T5A
Data Sheet
Advance Information*
8-Lane 5-Port
PCI Express® Switch
®
◆
Highly Integrated Solution
– Requires no external components
Device Overview
The 89HPES8T5A is a member of IDT’s PRECISE™ family of PCI
Express switching solutions. The PES8T5A is an 8-lane, 5-port periph-
eral chip that performs PCI Express Base switching. It provides connec-
tivity and switching functions between a PCI Express upstream port and
up to four downstream ports and supports switching between down-
stream ports.
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates eight 2.5 Gbps embedded SerDes with 8B/10B
encoder/decoder (no separate transceivers needed)
Reliability, Availability, and Serviceability (RAS) Features
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports ECRC and Advanced Error Reporting
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC mother-
boards
◆
◆
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Features
◆
High Performance PCI Express Switch
– Eight 2.5Gbps PCI Express lanes
– Five switch ports
– Upstream port is x4
– Downstream ports are x1
Power Management
– Utilizes advanced low-power design techniques to achieve low
typical power consumption
– Low-latency cut-through switch architecture
– Support for Max Payload Sizes up to 256 bytes
– One virtual channel
– Supports PCI Power Management Interface specification (PCI-
– Eight traffic classes
PM 1.2)
– PCI Express Base Specification Revision 1.1 compliant
Flexible Architecture with Numerous Configuration Options
– Unused SerDes are disabled.
◆
– Supports Advanced Configuration and Power Interface Speci-
fication, Revision 2.0 (ACPI) supporting active link state
– Automatic lane reversal on all ports
Testability and Debug Features
– Built in Pseudo-Random Bit Stream (PRBS) generator
– Numerous SerDes test modes
– Automatic polarity inversion on all lanes
– Ability to load device configuration from serial EEPROM
Legacy Support
◆
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
– PCI compatible INTx emulation
– Bus locking
Block Diagram
5-Port Switch Core / 8 PCI Express Lanes
Port
Frame Buffer
Route Table
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Mux / Demux
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Mux / Demux
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Mux / Demux
Mux / Demux
Mux / Demux
Phy
Phy
Phy
Phy
Phy
Logical
Layer
Logical
Layer
Logical
Layer
Logical
Layer
Logical
Layer
SerDes
SerDes
SerDes
SerDes
SerDes
(Port 2)
(Port 4)
(Port 5)
(Port 0)
(Port 3)
Figure 1 Internal Block Diagram
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September 7, 2007
© 2007 Integrated Device Technology, Inc.
*Notice: The information in this document is subject to change without notice