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89C51AC2-RLTUM PDF预览

89C51AC2-RLTUM

更新时间: 2024-01-03 22:10:20
品牌 Logo 应用领域
爱特美尔 - ATMEL 时钟ATM异步传输模式微控制器外围集成电路
页数 文件大小 规格书
121页 806K
描述
Microcontroller, 8-Bit, FLASH, 40MHz, CMOS, PQFP44, VQFP-44

89C51AC2-RLTUM 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP,针数:44
Reach Compliance Code:compliantECCN代码:3A991.A.2
HTS代码:8542.31.00.01风险等级:5.62
具有ADC:YES地址总线宽度:16
位大小:8最大时钟频率:40 MHz
DAC 通道:NODMA 通道:NO
外部数据总线宽度:8JESD-30 代码:S-PQFP-G44
JESD-609代码:e3长度:10 mm
I/O 线路数量:34端子数量:44
最高工作温度:85 °C最低工作温度:-40 °C
PWM 通道:YES封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):260
认证状态:Not QualifiedROM可编程性:FLASH
座面最大高度:1.6 mm速度:40 MHz
最大供电电压:5.5 V最小供电电压:3 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:10 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLERBase Number Matches:1

89C51AC2-RLTUM 数据手册

 浏览型号89C51AC2-RLTUM的Datasheet PDF文件第5页浏览型号89C51AC2-RLTUM的Datasheet PDF文件第6页浏览型号89C51AC2-RLTUM的Datasheet PDF文件第7页浏览型号89C51AC2-RLTUM的Datasheet PDF文件第9页浏览型号89C51AC2-RLTUM的Datasheet PDF文件第10页浏览型号89C51AC2-RLTUM的Datasheet PDF文件第11页 
Table 2. Read-Modify-Write Instructions  
Instruction  
Description  
Example  
ANL  
logical AND  
ANL P1, A  
ORL P2, A  
XRL P3, A  
JBC P1.1, LABEL  
CPL P3.0  
ORL  
logical OR  
XRL  
logical EX-OR  
JBC  
jump if bit = 1 and clear bit  
complement bit  
CPL  
INC  
increment  
INC P2  
DEC  
decrement  
DEC P2  
DJNZ  
decrement and jump if not zero  
move carry bit to bit y of Port x  
clear bit y of Port x  
set bit y of Port x  
DJNZ P3, LABEL  
MOV P1.5, C  
CLR P2.4  
MOV Px.y, C  
CLR Px.y  
SET Px.y  
SET P3.3  
It is not obvious the last three instructions in this list are Read-Modify-Write instructions.  
These instructions read the port (all 8 bits), modify the specifically addressed bit and  
write the new byte back to the latch. These Read-Modify-Write instructions are directed  
to the latch rather than the pin in order to avoid possible misinterpretation of voltage  
(and therefore, logic) levels at the pin. For example, a Port bit used to drive the base of  
an external bipolar transistor can not rise above the transistor’s base-emitter junction  
voltage (a value lower than VIL). With a logic one written to the bit, attempts by the CPU  
to read the Port at the pin are misinterpreted as logic zero. A read of the latch rather  
than the pins returns the correct logic-one value.  
Quasi-Bidirectional Port Port 1, Port 2, Port 3 and Port 4 have fixed internal pull-ups and are referred to as  
"quasi-bidirectional" Ports. When configured as an input, the pin impedance appears as  
Operation  
logic one and sources current in response to an external logic zero condition. Port 0 is a  
"true bidirectional" pin. The pins float when configured as input. Resets write logic one to  
all Port latches. If logical zero is subsequently written to a Port latch, it can be returned  
to input conditions by a logical one written to the latch.  
Note:  
Port latch values change near the end of Read-Modify-Write instruction cycles. Output  
buffers (and therefore the pin state) update early in the instruction after Read-Modify-  
Write instruction cycle.  
Logical zero-to-one transitions in Port 1, Port 2, Port 3 and Port 4 use an additional pull-  
up (p1) to aid this logic transition (see Figure 4.). This increases switch speed. This  
extra pull-up sources 100 times normal internal circuit current during 2 oscillator clock  
periods. The internal pull-ups are field-effect transistors rather than linear resistors. Pull-  
ups consist of three p-channel FET (pFET) devices. A pFET is on when the gate senses  
logical zero and off when the gate senses logical one. pFET #1 is turned on for two  
oscillator periods immediately after a zero-to-one transition in the Port latch. A logical  
one at the Port pin turns on pFET #3 (a weak pull-up) through the inverter. This inverter  
and pFET pair form a latch to drive logical one. pFET #2 is a very weak pull-up switched  
on whenever the associated nFET is switched off. This is traditional CMOS switch con-  
vention. Current strengths are 1/10 that of pFET #3.  
8
A/T89C51AC2  
4127G–8051–05/06  
 

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