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89C51AC2-RLTUM PDF预览

89C51AC2-RLTUM

更新时间： 2024-02-08 22:43:18
品牌 Logo 应用领域
爱特美尔 - ATMEL 时钟ATM异步传输模式微控制器外围集成电路
页数 文件大小 规格书
121页 806K
描述
Microcontroller, 8-Bit, FLASH, 40MHz, CMOS, PQFP44, VQFP-44

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89C51AC2-RLTUM 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP,针数：44
Reach Compliance Code：compliantECCN代码：3A991.A.2
HTS代码：8542.31.00.01风险等级：5.62
具有ADC：YES地址总线宽度：16
位大小：8最大时钟频率：40 MHz
DAC 通道：NODMA 通道：NO
外部数据总线宽度：8JESD-30 代码：S-PQFP-G44
JESD-609代码：e3长度：10 mm
I/O 线路数量：34端子数量：44
最高工作温度：85 °C最低工作温度：-40 °C
PWM 通道：YES封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE峰值回流温度（摄氏度）：260
认证状态：Not QualifiedROM可编程性：FLASH
座面最大高度：1.6 mm速度：40 MHz
最大供电电压：5.5 V最小供电电压：3 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.8 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：10 mm
uPs/uCs/外围集成电路类型：MICROCONTROLLERBase Number Matches：1

89C51AC2-RLTUM 数据手册

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A/T89C51AC2  
Table 1. Pin Description (Continued)  
Pin Name  
Type  
Description  
P3.0:7  
I/O  
Port 3:  
Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them are pulled high by the internal  
pull-up transistors and can be used as inputs in this state. As inputs, Port 3 pins that are being pulled low externally will be a  
source of current (IIL, see section "Electrical Characteristic") because of the internal pull-ups.  
The output latch corresponding to a secondary function must be programmed to one for that function to operate (except for  
TxD and WR). The secondary functions are assigned to the pins of port 3 as follows:  
P3.0/RxD:  
Receiver data input (asynchronous) or data input/output (synchronous) of the serial interface  
P3.1/TxD:  
Transmitter data output (asynchronous) or clock output (synchronous) of the serial interface  
P3.2/INT0:  
External interrupt 0 input/timer 0 gate control input  
P3.3/INT1:  
External interrupt 1 input/timer 1 gate control input  
P3.4/T0:  
Timer 0 counter input  
P3.5/T1:  
Timer 1 counter input  
P3.6/WR:  
External Data Memory write strobe; latches the data byte from port 0 into the external data memory  
P3.7/RD:  
External Data Memory read strobe; Enables the external data memory.  
It can drive CMOS inputs without external pull-ups.  
P4.0:1  
I/O  
Port 4:  
Is an 2-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1’s written to them are pulled high by the internal  
pull-ups and can be used as inputs in this state. As inputs, Port 4 pins that are being pulled low externally will be a source of  
current (IIL, on the datasheet) because of the internal pull-up transistor.  
P4.0  
P4.1:  
It can drive CMOS inputs without external pull-ups.  
Reset:  
RESET  
ALE  
I/O  
O
A high level on this pin during two machine cycles while the oscillator is running resets the device. An internal pull-down  
resistor to VSS permits power-on reset using only an external capacitor to VCC.  
ALE:  
An Address Latch Enable output for latching the low byte of the address during accesses to the external memory. The ALE is  
activated every 1/6 oscillator periods (1/3 in X2 mode) except during an external data memory access. When instructions are  
executed from an internal Flash (EA = 1), ALE generation can be disabled by the software.  
PSEN:  
The Program Store Enable output is a control signal that enables the external program memory of the bus during external  
fetch operations. It is activated twice each machine cycle during fetches from the external program memory. However, when  
executing from of the external program memory two activations of PSEN are skipped during each access to the external Data  
memory. The PSEN is not activated for internal fetches.  
PSEN  
EA  
O
I
EA:  
When External Access is held at the high level, instructions are fetched from the internal Flash when the program counter is  
less then 8000H. When held at the low level,A/T89C51AC2 fetches all instructions from the external program memory.  
XTAL1:  
Input of the inverting oscillator amplifier and input of the internal clock generator circuits.  
To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To operate  
above a frequency of 16 MHz, a duty cycle of 50% should be maintained.  
XTAL1  
XTAL2  
I
XTAL2:  
O
Output from the inverting oscillator amplifier.  
5
4127G–8051–05/06  
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