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89C51AC2-RLTUM

更新时间： 2024-01-30 16:46:17
品牌 Logo 应用领域
爱特美尔 - ATMEL 时钟ATM异步传输模式微控制器外围集成电路
页数 文件大小 规格书
121页 806K
描述
Microcontroller, 8-Bit, FLASH, 40MHz, CMOS, PQFP44, VQFP-44

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89C51AC2-RLTUM 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP,针数：44
Reach Compliance Code：compliantECCN代码：3A991.A.2
HTS代码：8542.31.00.01风险等级：5.62
具有ADC：YES地址总线宽度：16
位大小：8最大时钟频率：40 MHz
DAC 通道：NODMA 通道：NO
外部数据总线宽度：8JESD-30 代码：S-PQFP-G44
JESD-609代码：e3长度：10 mm
I/O 线路数量：34端子数量：44
最高工作温度：85 °C最低工作温度：-40 °C
PWM 通道：YES封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE峰值回流温度（摄氏度）：260
认证状态：Not QualifiedROM可编程性：FLASH
座面最大高度：1.6 mm速度：40 MHz
最大供电电压：5.5 V最小供电电压：3 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.8 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：10 mm
uPs/uCs/外围集成电路类型：MICROCONTROLLERBase Number Matches：1

89C51AC2-RLTUM 数据手册

 浏览型号89C51AC2-RLTUM的Datasheet PDF文件第3页浏览型号89C51AC2-RLTUM的Datasheet PDF文件第4页浏览型号89C51AC2-RLTUM的Datasheet PDF文件第5页浏览型号89C51AC2-RLTUM的Datasheet PDF文件第7页浏览型号89C51AC2-RLTUM的Datasheet PDF文件第8页浏览型号89C51AC2-RLTUM的Datasheet PDF文件第9页 
I/O Configurations  
Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A  
CPU "write to latch" signal initiates transfer of internal bus data into the type-D latch. A  
CPU "read latch" signal transfers the latched Q output onto the internal bus. Similarly, a  
"read pin" signal transfers the logical level of the Port pin. Some Port data instructions  
activate the "read latch" signal while others activate the "read pin" signal. Latch instruc-  
tions are referred to as Read-Modify-Write instructions. Each I/O line may be  
independently programmed as input or output.  
Port 1, Port 3 and Port 4  
Figure 1 shows the structure of Ports 1 and 3, which have internal pull-ups. An external  
source can pull the pin low. Each Port pin can be configured either for general-purpose  
I/O or for its alternate input output function.  
To use a pin for general-purpose output, set or clear the corresponding bit in the Px reg-  
ister (x = 1,3 or 4). To use a pin for general-purpose input, set the bit in the Px register.  
This turns off the output FET drive.  
To configure a pin for its alternate function, set the bit in the Px register. When the latch  
is set, the "alternate output function" signal controls the output level (see Figure 1). The  
operation of Ports 1, 3 and 4 is discussed further in the "quasi-Bidirectional Port Opera-  
tion" section.  
Figure 1. Port 1, Port 3 and Port 4 Structure  
VCC  
ALTERNATE  
INTERNAL  
PULL-UP (1)  
OUTPUT  
FUNCTION  
READ  
LATCH  
P1.x  
P3.x  
P4.x  
INTERNAL  
BUS  
D P1.X  
P3.X  
Q
P4.X  
LATCH  
WRITE  
TO  
LATCH  
CL  
READ  
PIN  
ALTERNATE  
INPUT  
FUNCTION  
Note:  
The internal pull-up can be disabled on P1 when analog function is selected.  
Port 0 and Port 2  
Ports 0 and 2 are used for general-purpose I/O or as the external address/data bus. Port  
0, shown in Figure 3, differs from the other Ports in not having internal pull-ups. Figure 3  
shows the structure of Port 2. An external source can pull a Port 2 pin low.  
To use a pin for general-purpose output, set or clear the corresponding bit in the Px reg-  
ister (x = 0 or 2). To use a pin for general-purpose input, set the bit in the Px register to  
turn off the output driver FET.  
6
A/T89C51AC2  
4127G–8051–05/06  
 
 
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