88C37-AF5-R

更新时间： 2024-01-22 03:21:20

品牌	Logo	应用领域
友顺 - UTC		电源电路电源管理电路光电二极管
页数	文件大小	规格书
16页	216K
描述
BUILT-IN DELAY CIRCUIT HIGH-PRECISION VOLTAGE DETECTOR

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88C37-AF5-R 技术参数

生命周期：	Active	零件包装代码：	SOT
包装说明：	LSSOP,	针数：	5
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.13
可调阈值：	NO	模拟集成电路 - 其他类型：	POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：	R-PDSO-G5	长度：	2.9 mm
信道数量：	1	功能数量：	1
端子数量：	5	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH	座面最大高度：	1.45 mm
最大供电电压 (Vsup)：	10 V	最小供电电压 (Vsup)：	0.95 V
标称供电电压 (Vsup)：	3.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.95 mm
端子位置：	DUAL	宽度：	1.6 mm
Base Number Matches：	1

88C37-AF5-R 数据手册

88CXX

CMOS IC

ꢀ

OPERATION

1. Basic operation: CMOS active low output

(1) When power supply voltage V_DDis greater than the release voltage +V_DET, the Nch transistor is OFF and the

Pch transistor ON, causing V_DD(high) to appear at the output.

(2) When power supply voltage V_DDgoes below +V_DET, the output maintains the power supply voltage level, as

long as V_DDremains above the detection voltage -V_DET. When V_DDdoes fall below -V_DET(A in Figure 7), the Nch

transistor goes ON the Pch transistor goes OFF, and V_SSappears at the output.

(3) When V_DDfalls below the minimum operating voltage, the output becomes undefined. However, output will

revert to V_DDif a pull-up has been employed.

(4) V_SSwill again be output when V_DDrises above the minimum operating voltage. V_SSwill continue to be output

even when V_DDsurpasses -V_DET, as long as it does not exceed the release voltage +V_DET

(5) When V_DDrises above +V_DET(B in Figure 7), the Nch transistor goes OFF the Pch transistor goes ON, and V_DD

appears at the output. Then V_DDat the OUT terminal appears with delay time (td) due to delay circuit.

VDD

(1)

(2)

(3)

(4)

(5)

V^DD

Hysteresis

width(V^HYS)

Release voltage (+V^DET)

Detection voltage (-V^DET)

Pch

Nch

Delay

circuit

Min.operating voltage

V^ss

OUT

C^D

VREF

Vss

V^DD

*Parasitic diode

OUT terminal output

Vss

Figure 6

Figure 7

2. Delay circuit

The delay circuit outputs the signal delayed from the release voltage (+V_DET) point of the power voltage V_DD

rising. The output signal is not delayed when the V_DDgoes down the detection voltage (-V_DET) or less. (See Figure 7).

The delay time (td) is determined by the time constant of the built-in constant current (approx. 100nA in the case

of products with detection voltage of 1.5V or more, approx. 570nA in the case of products with detection voltage of

1.4V or less) and the attached external capacitor (C_D), and calculated from the following formula.

td (ms) = Delay factor×C_D(nF)

Delay factor: (25℃)

Products with detection voltage of 1.4V or less: Min.0.57, Typ.0.77, Max.0.96

Products with detection voltage of 1.5V or more: Min.3.8, Typ. 5.1, Max.6.4

UNISONIC TECHNOLOGIES CO., LTD

www.unisonic.com.tw

QW-R502-040,A

1...6 7 8910 11 12...16

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88C38-AF5-R	UTC	BUILT-IN DELAY CIRCUIT HIGH-PRECISION VOLTAGE DETECTOR	获取价格
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