87C196KT/87C196KS
ADVANCED 16-BIT CHMOS MICROCONTROLLER
Automotive
b
a
(
40 Cto
§
125 C Ambient)
§
Y
Y
Y
Y
Y
High Performance CHMOS 16-Bit CPU
Up to 32 Kbytes of On-Chip EPROM
High Speed Peripheral Transaction
Server (PTS)
Y
Two Dedicated 16-Bit High-Speed
Compare Registers
Up to 1 Kbyte of On-Chip Register RAM
Up to 512 Bytes of Additional RAM
(Code RAM)
Y
Y
10 High Speed Capture/Compare (EPA)
Full Duplex Synchronous Serial I/O
Port (SSIO)
Y
Y
Y
Y
Y
Y
Y
Register-Register Architecture
8 Channel/10-Bit A/D with Sample/Hold
37 Prioritized Interrupt Sources
Up to Seven 8-Bit (56) I/O Ports
Full Duplex Serial I/O Port
Y
Y
Y
Two Flexible 16-Bit Timer/Counters
Quadrature Counting Inputs
Flexible 8-/16-Bit External Bus
(Programmable)
Dedicated Baud Rate Generator
Y
Y
Y
Y
Programmable Bus (HLD/HLDA)
1.75 ms 16 x 16 Multiply
3 ms 32/16 Divide
Interprocessor Communication Slave
Port
Y
Y
Selectable Bus Timing Modes for
Flexible Interfacing
68-Pin PLCC Package
Oscillator Fail Detection Circuitry
The 87C196Kx devices represents the 4th generation of MCS 96 microcontroller products implemented on
É
Intel’s advanced 1 micron process technology. These products are based on the 80C196KB device with
enhancements ideal for automotive applications. The instruction set is a true super set of the 80C196KB with a
few new instructions.
The MCS 96 microcontroller family members are all high performance microcontrollers with a 16-bit CPU. The
87C196KT is composed of the high speed (16 MHz) KX macrocore as well as the following peripherals: Up to
32 Kbytes of Program EPROM, up to 1 Kbytes of Register RAM (00-3FFH including SFRs), up to 512 bytes of
code RAM (16-bit addressing modes) with the ability to execute from this RAM space, an eight channel-10 Bit
k
g
3LSB analog to digital converter with programmable S/H times with conversion times 20 ms at 16 MHz, an
asynchronous/synchronous serial I/O port (8096 compatable) with a dedicated 16-bit baud rate generator, an
additional synchronous serial I/O port with full duplex master/slave transceivers, a flexible timer/counter
structure with prescaler, cascading, and quadrature capabilities, 10 modularized multiplexed high speed I/O
for capture and compare (called Event Processor Array) with 250 ns resolution and double buffered inputs,
and a sophisticated prioritized interrupt structure with programmable Peripheral Transaction Server (PTS). The
PTS has several channel modes, including single/burst block transfers from any memory location to any
memory location, a PWM and PWM toggle mode to be used in conjunction with the EPA, and an A/D scan
mode.
Additional SFR space is allocated for the EPA and can be ‘‘windowed’’ into the lower Register RAM area.
NOTICE:
This datasheet contains information on products in production. The specifications are subject to change
without notice. Verify with your local Intel Sales office that you have the latest data sheet before finalizing a
design.
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
November 1995
COPYRIGHT INTEL CORPORATION, 1995
Order Number: 270999-007
©
1