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8634BY-01LFT PDF预览

8634BY-01LFT

更新时间： 2024-01-07 08:14:30
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
17页 284K
描述
TQFP-32, Reel

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8634BY-01LFT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TQFP
包装说明：7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32针数：32
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.82
系列：8634输入调节：DIFFERENTIAL MUX
JESD-30 代码：S-PQFP-G32JESD-609代码：e3
长度：7 mm逻辑集成电路类型：PLL BASED CLOCK DRIVER
湿度敏感等级：3功能数量：1
反相输出次数：端子数量：32
实输出次数：5最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP32,.35SQ,32
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE
峰值回流温度（摄氏度）：260电源：3.3 V
Prop。Delay @ Nom-Sup：4.2 ns传播延迟（tpd）：4.2 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.025 ns
座面最大高度：1.6 mm子类别：Clock Drivers
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：COMMERCIAL端子面层：Matte Tin (Sn) - annealed
端子形式：GULL WING端子节距：0.8 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7 mm最小 fmax：700 MHz
Base Number Matches：1

8634BY-01LFT 数据手册

 浏览型号8634BY-01LFT的Datasheet PDF文件第6页浏览型号8634BY-01LFT的Datasheet PDF文件第7页浏览型号8634BY-01LFT的Datasheet PDF文件第8页浏览型号8634BY-01LFT的Datasheet PDF文件第10页浏览型号8634BY-01LFT的Datasheet PDF文件第11页浏览型号8634BY-01LFT的Datasheet PDF文件第12页 
ICS8634-01  
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL  
ZERO DELAY BUFFER  
The following component footprints are used in this layout  
example:  
trace and the trace delay might be restricted by the available  
space on the board and the component location. While routing  
the traces, the clock signal traces should be routed first and  
should be locked prior to routing other signal traces.  
All the resistors and capacitors are size 0603.  
POWER AND GROUNDING  
•
The differential 50output traces should have same  
Place the decoupling capacitors C1, C2, C4, C5, C6, and C7, as  
close as possible to the power pins. If space allows, placement  
of the decoupling capacitor on the component side is preferred.  
This can reduce unwanted inductance between the decoupling  
capacitor and the power pin caused by the via.  
length.  
•
Avoid sharp angles on the clock trace.Sharp angle turns  
cause the characteristic impedance to change on  
the transmission lines.  
•
•
Keep the clock traces on the same layer.Whenever pos-  
sible, avoid placing vias on the clock traces. Placement  
of vias on the traces can affect the trace characteristic  
impedance and hence degrade signal integrity.  
Maximize the power and ground pad sizes and number of vias  
capacitors.This can reduce the inductance between the power  
and ground planes and the component power and ground pins.  
To prevent cross talk, avoid routing other signal traces  
in parallel with the clock traces.If running parallel traces  
is unavoidable, allow a separation of at least three trace  
widths between the differential clock trace and the other  
signal trace.  
The RC filter consisting of R7, C11, and C16 should be placed  
as close to the VCCA pin as possible.  
CLOCK TRACES AND TERMINATION  
Poor signal integrity can degrade the system performance or  
cause system failure. In synchronous high-speed digital sys-  
tems, the clock signal is less tolerant to poor signal integrity  
than other signals. Any ringing on the rising or falling edge or  
excessive ring back can cause system failure.The shape of the  
•
•
Make sure no other signal traces are routed between  
the clock trace pair.  
The matching termination resistors should be located as  
close to the receiver input pins as possible.  
FIGURE 5B. PCB BOARD LAYOUT FOR ICS8634-01  
www.idt.com  
8634BY-01  
9
REV. D MAY 12, 2014  
1...6789101112...17

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