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8634BY-01LFT PDF预览

8634BY-01LFT

更新时间: 2024-01-29 10:33:58
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
17页 284K
描述
TQFP-32, Reel

8634BY-01LFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TQFP
包装说明:7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32针数:32
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.82
系列:8634输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G32JESD-609代码:e3
长度:7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:5最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:4.2 ns传播延迟(tpd):4.2 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.025 ns
座面最大高度:1.6 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7 mm最小 fmax:700 MHz
Base Number Matches:1

8634BY-01LFT 数据手册

 浏览型号8634BY-01LFT的Datasheet PDF文件第4页浏览型号8634BY-01LFT的Datasheet PDF文件第5页浏览型号8634BY-01LFT的Datasheet PDF文件第6页浏览型号8634BY-01LFT的Datasheet PDF文件第8页浏览型号8634BY-01LFT的Datasheet PDF文件第9页浏览型号8634BY-01LFT的Datasheet PDF文件第10页 
ICS8634-01  
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL  
ZERO DELAY BUFFER  
POWER SUPPLY FILTERING TECHNIQUES  
As in any high speed analog circuitry, the power supply  
pins are vulnerable to random noise. The ICS8634-01 pro-  
vides separate power supplies to isolate any high switching  
noise from the outputs to the internal PLL. VCC, VCCA, and  
VCCO should be individually connected to the power supply  
plane through vias, and bypass capacitors should be  
used for each pin. To achieve optimum jitter performance,  
power supply isolation is required. Figure 3 illustrates how  
a 10Ω resistor along with a 10μF and a .01μF bypass  
capacitor should be connected to each VCCA pin.  
FIGURE 3. POWER SUPPLY FILTERING  
DIFFERENTIAL CLOCK INPUT INTERFACE  
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL  
component to confirm the driver termination requirements. For  
example in Figure 4A, the input termination applies for LVH-  
STL drivers. If you are using an LVHSTL driver from another  
vendor, use their termination recommendation.  
SWING  
OH  
and other differential signals. Both V  
and V must meet  
input requirements. Figures 4A to 4D show  
PP  
CMR  
the V and V  
interface examples for the CLK/nCLK input driven by the most  
common driver types.The input interfaces suggested here are  
examples only. Please consult with the vendor of the driver  
3.3V  
3.3V  
3.3V  
1.8V  
Zo = 50 Ohm  
CLK  
Zo = 50 Ohm  
CLK  
Zo = 50 Ohm  
nCLK  
Zo = 50 Ohm  
HiPerClockS  
Input  
LVPECL  
nCLK  
HiPerClockS  
Input  
LVHSTL  
R1  
50  
R2  
50  
ICS  
R1  
50  
R2  
50  
HiPerClockS  
LVHSTL Driver  
R3  
50  
FIGURE 4A. CLK/nCLK INPUT DRIVEN BY  
LVHSTL DRIVER  
FIGURE 4B. CLK/nCLK INPUT DRIVEN BY  
3.3V LVPECL DRIVER  
3.3V  
3.3V  
3.3V  
3.3V  
3.3V  
Zo = 50 Ohm  
R3  
125  
R4  
125  
Zo = 50 Ohm  
Zo = 50 Ohm  
LVDS_Driver  
CLK  
CLK  
R1  
100  
nCLK  
nCLK  
Receiver  
HiPerClockS  
Input  
LVPECL  
Zo = 50 Ohm  
R1  
84  
R2  
84  
FIGURE 4C. CLK/nCLK INPUT DRIVEN BY  
3.3V LVPECL DRIVER  
FIGURE 4D. CLK/nCLK INPUT DRIVEN BY  
3.3V LVDS DRIVER  
8634BY-01  
7
www.idt.com  
REV. D MAY 12, 2014  

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