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8607601EA PDF预览

8607601EA

更新时间: 2024-10-31 21:53:59
品牌 Logo 应用领域
德州仪器 - TI 计数器触发器逻辑集成电路
页数 文件大小 规格书
24页 637K
描述
4-BIT SYNCHRONOUS BINARY COUNTERS

8607601EA 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP-16针数:16
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.11Is Samacsys:N
其他特性:RCO OUTPUT计数方向:UP
系列:HC/UHJESD-30 代码:R-GDIP-T16
长度:19.56 mm负载电容(CL):50 pF
负载/预设输入:YES逻辑集成电路类型:BINARY COUNTER
最大频率@ Nom-Sup:21000000 Hz最大I(ol):0.0052 A
工作模式:SYNCHRONOUS位数:4
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
最大电源电流(ICC):0.08 mAProp。Delay @ Nom-Sup:46 ns
传播延迟(tpd):310 ns认证状态:Qualified
筛选级别:MIL-PRF-38535座面最大高度:5.08 mm
子类别:Counter最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:6.92 mm最小 fmax:25 MHz
Base Number Matches:1

8607601EA 数据手册

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ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ ꢀꢁꢊ ꢃꢄ ꢅꢆ ꢇꢈ  
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SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003  
SN54HC163 . . . J OR W PACKAGE  
SN74HC163 . . . D, DB, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
D
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V  
Outputs Can Drive Up To 10 LSTTL Loads  
Low Power Consumption, 80-µA Max I  
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CLR  
CLK  
A
V
CC  
RCO  
Typical t = 14 ns  
pd  
4-mA Output Drive at 5 V  
Q
Q
Q
Q
A
B
C
D
Low Input Current of 1 µA Max  
Internal Look-Ahead for Fast Counting  
Carry Output for n-Bit Cascading  
Synchronous Counting  
B
C
D
ENP  
GND  
ENT  
LOAD  
Synchronously Programmable  
SN54HC163 . . . FK PACKAGE  
(TOP VIEW)  
description/ordering information  
These synchronous, presettable counters feature  
an internal carry look-ahead for application in  
high-speed counting designs. The ’HC163  
devices are 4-bit binary counters. Synchronous  
operation is provided by having all flip-flops  
clocked simultaneously so that the outputs  
change coincident with each other when  
instructed by the count-enable (ENP, ENT) inputs  
and internal gating. This mode of operation  
eliminates the output counting spikes normally  
associated with synchronous (ripple-clock)  
counters. A buffered clock (CLK) input triggers the  
four flip-flops on the rising (positive-going) edge of  
the clock waveform.  
3
2
1
20 19  
18  
A
B
Q
Q
4
5
6
7
8
A
B
17  
16  
15  
14  
NC  
C
NC  
Q
Q
C
D
D
9 10 11 12 13  
NC − No internal connection  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
SOIC − D  
Tube of 25  
Tube of 40  
Reel of 2500  
Reel of 250  
Reel of 2000  
Reel of 2000  
Tube of 90  
Reel of 2000  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HC163N  
SN74HC163N  
SN74HC163D  
SN74HC163DR  
SN74HC163DT  
SN74HC163NSR  
SN74HC163DBR  
SN74HC163PW  
SN74HC163PWR  
SN74HC163PWT  
SNJ54HC163J  
HC163  
SOP − NS  
HC163  
HC163  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
HC163  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HC163J  
SNJ54HC163W  
SNJ54HC163FK  
−55°C to 125°C  
SNJ54HC163W  
SNJ54HC163FK  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢑ ꢘ ꢣ ꢛ ꢚꢦ ꢡꢠ ꢞꢟ ꢠꢚ ꢜꢣ ꢥꢗ ꢝꢘ ꢞ ꢞꢚ ꢭꢍ ꢮꢋ ꢕꢐ ꢯ ꢋꢈꢰꢂ ꢈꢂꢉ ꢝꢥꢥ ꢣꢝ ꢛ ꢝ ꢜꢢ ꢞꢢꢛ ꢟ ꢝ ꢛ ꢢ ꢞꢢ ꢟꢞꢢ ꢦ  
ꢞ ꢢ ꢟ ꢞꢗ ꢘꢬ ꢚꢙ ꢝ ꢥꢥ ꢣꢝ ꢛ ꢝ ꢜ ꢢ ꢞ ꢢ ꢛ ꢟ ꢧ  
ꢡ ꢘꢥ ꢢꢟꢟ ꢚ ꢞꢨꢢ ꢛ ꢪꢗ ꢟꢢ ꢘ ꢚꢞꢢ ꢦꢧ ꢑ ꢘ ꢝꢥ ꢥ ꢚ ꢞꢨꢢ ꢛ ꢣꢛ ꢚ ꢦꢡꢠ ꢞꢟ ꢉ ꢣꢛ ꢚ ꢦꢡꢠ ꢞꢗꢚ ꢘ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

8607601EA 替代型号

型号 品牌 替代类型 描述 数据表
CD74HC163M TI

完全替代

High Speed CMOS Logic Presettable Counters
CD74HC163E TI

完全替代

High Speed CMOS Logic Presettable Counters
CD74HC163M96 TI

完全替代

High-Speed CMOS Logic Presettable Counters

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