Datasheet > 854S006I

854S006I

更新时间： 2023-12-20 18:44:11

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
18页	1090K
描述
Low Skew,1-to-6,Differential-to-LVDS Fanout Buffer

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854S006I 数据手册

854S006 Datasheet

Applications Information

Recommendations for Unused Input and Output Pins

Outputs:

LVDS Outputs

Any unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating there should be no trace

attached.

Wiring the Differential Input to Accept Single-ended Levels

Figure 12 shows how a differential input can be wired to accept single ended levels. The reference voltage V_REF= V_DD/2 is generated by

the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as

close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V_REFin the center of the input voltage

swing. For example, if the input clock swing is 2.5V and V_DD= 3.3V, R1 and R2 value should be adjusted to set V_REFat 1.25V. The values

below are for when both the single ended swing and V_DDare at the same voltage. This configuration requires that the sum of the output

impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at

the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission

line impedance. For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading

for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are

reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The

datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the

swing can be larger, however V_ILcannot be less than -0.3V and V_IHcannot be more than V_DD+0.3V. Suggest edge rate faster than

1V/ns. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized

for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal.

Figure 12. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels

April 11, 2017

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型号	品牌	描述	获取价格	数据表
854S013BGLF	IDT	Clock Driver, S Series, 3 True Output(s), 3 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.	获取价格
854S013BGLFT	IDT	Clock Driver, S Series, 3 True Output(s), 3 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.	获取价格
854S013I	IDT	Clock Driver	获取价格
854S013ILF	IDT	Clock Driver	获取价格
854S013ILFT	IDT	Clock Driver	获取价格
854S015CG-01LF	IDT	Clock Driver, 854S Series, 5 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 X 7.80 MM,	获取价格