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853S6111AYILF PDF预览

853S6111AYILF

更新时间: 2024-02-15 19:12:50
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
24页 431K
描述
PTQFP-32, Tray

853S6111AYILF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:PTQFP
包装说明:7 X 7 MM, 1 MM HEIGHT, ROHS COMPLIANT, MS-026ABC-HD, TQFP-32针数:32
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.81
其他特性:ALSO OPERATES AT 3.3 V SUPPLY系列:853
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-PQFP-G32
JESD-609代码:e3长度:7 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER最大I(ol):0.005 A
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:10最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:HTQFP封装等效代码:TQFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK, HEAT SINK/SLUG, THIN PROFILE
峰值回流温度(摄氏度):260电源:+-2.5/+-3.3 V
Prop。Delay @ Nom-Sup:0.53 ns传播延迟(tpd):0.53 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.035 ns
座面最大高度:1.2 mm子类别:Clock Drivers
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:7 mmBase Number Matches:1

853S6111AYILF 数据手册

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ICS853S6111I Data Sheet  
LOW VOLTAGE, 1-TO-10 DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER  
DC Electrical Characteristics  
Table 5A. LVPECL (PCLK, nPCLK), HSTL (CLK, nCLK) DC Characteristics, VCC = 3.3V 5ꢀ or 2.5V 5ꢀ; VEE = 0V,  
TA = -40°C to 85°C  
Symbol  
Parameter  
Test Conditions  
VIN = VIL or VIN = VIH  
VIN = VIL or VIN = VIH  
Minimum  
Typical  
Maximum  
Units  
Control Input CLK_SEL  
VIL  
VIH  
IIN  
Input Low Voltage  
VCC - 1.810  
VCC - 1.165  
VCC - 1.475  
VCC - 0.880  
100  
V
V
Input High Voltage  
Input Current; NOTE 1  
µA  
Clock Input Pair PCLK, nPCLK  
VPP  
VCMR  
IIN  
Differential Input Voltage; NOTE 2  
0.1  
1.0  
1.3  
VCC - 0.3  
100  
V
V
Differential Cross Point Voltage; NOTE 3  
Input Current; NOTE 1  
µA  
Clock Input Pair CLK, nCLK  
VDIF  
VX  
Differential Input Voltage; NOTE 4, 7  
0.4  
0
1.0  
VCC - 1.1  
200  
V
V
Differential Crosspoint Voltage; NOTE 5  
Input Current  
0.68 - 0.9  
IIN  
VIN = Vx 0.2V  
IOH = -30mA  
µA  
PECL Clock Outputs  
VOH Output High Voltage; NOTE 6  
VCC - 1.2  
VCC - 1.9  
VCC - 1.005  
VCC - 1.705  
VCC - 0.7  
VCC - 1.5  
V
V
VCC = 3.3V 5ꢀ,  
IOL = -5mA  
VOL  
Output Low Voltage; NOTE 6  
VCC = 2.5V 5ꢀ,  
OL = -5mA  
VCC - 1.9  
VCC - 1.705  
VCC - 1.3  
V
I
Supply Current and VBB  
Maximum Quiescent Supply Current  
without Output Termination Current  
IEE  
V
EE pin  
100  
mA  
V
VBB  
Output Reference Voltage  
IBB = 200µA  
VCC - 1.4  
VCC - 1.2  
NOTE 1: Inputs have internal pullup/pulldown resistors which affect the input current.  
NOTE 2: VPP (DC) is the minimum differential input voltage swing required to maintain device functionality.  
NOTE 3: VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR  
(DC) range and the input swing lies within the VPP (DC) specification.  
NOTE 4: VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality.  
NOTE 5: VX (DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX  
(DC) range and the input swing lies within the VPP (DC) specification.  
NOTE 6: Equivalent to a termination of 50to VTT equal to VCC/2.  
NOTE 7: For single-ended applications, the maximum input voltage for PCLK, nPCLK and CLK, nCLK is VCC + 0.3V.  
ICS853S6111AYI REVISION A FEBRUARY 6, 2013  
4
©2013 Integrated Device Technology, Inc.  

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