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853S202AYI

更新时间： 2023-01-03 10:01:58
品牌 Logo 应用领域
艾迪悌 - IDT /
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20页 559K
描述
Clock Driver

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853S202AYI 数据手册

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ICS853S202I  
12:2, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL MULTIPLEXER  
PRELIMINARY  
TABLE 1. PIN DESCRIPTIONS (CONTINUED ON NEXT PAGE)  
Number  
Name  
Type  
Pullup  
Description  
1
CLK2  
Input  
Input  
Non-inverting differential clock input.  
Pullup/  
Pulldown  
2
nCLK2  
Inverting differential clock input. VCC/2 default when left floating.  
3,  
4,  
9,  
SELA_0,  
SELA_1,  
SELA_2,  
SELA_3  
Clock select pins for Bank A outputs. See Control Input  
Pulldown Function Table. LVCMOS/LVTTL interface levels.  
See Table 3B.  
Input  
10  
5, 18, 32, 43  
VCC  
QA, nQA  
VEE  
Power  
Output  
Power  
Input  
Positive supply pins.  
6, 7  
8, 15, 22, 29, 39, 46  
11  
Clock outputs. LVDS interface levels.  
Negative supply pins.  
CLK3  
Pullup  
Non-inverting differential clock input.  
Pullup/  
Pulldown  
Pullup/  
12  
nCLK3  
Input  
Inverting differential clock input. VCC/2 default when left floating.  
13  
14  
16  
17  
19  
nCLK4  
CLK4  
nCLK5  
CLK5  
OEA  
Input  
Input  
Input  
Input  
Input  
Inverting differential clock input. VCC/2 default when left floating.  
Non-inverting differential clock input.  
Pulldown  
Pullup  
Pullup/  
Pulldown  
Inverting differential clock input. VCC/2 default when left floating.  
Pullup  
Non-inverting differential clock input.  
Output enable pin. Controls enabling and disabling of QA/nQA  
outputs. LVCMOS/LVTTL internface levels.  
Pullup  
Pullup/  
Pulldown  
20  
nCLK6  
Input  
Inverting differential clock input. VCC/2 default when left floating.  
21  
23  
CLK6  
CLK7  
Input  
Input  
Pullup  
Pullup  
Non-inverting differential clock input.  
Non-inverting differential clock input.  
Pullup/  
Pulldown  
Pullup/  
24  
nCLK7  
Input  
Inverting differential clock input. VCC/2 default when left floating.  
25  
26  
nCLK8  
CLK8  
Input  
Input  
Inverting differential clock input. VCC/2 default when left floating.  
Non-inverting differential clock input.  
Pulldown  
Pullup  
27,  
28,  
33,  
34  
SELB_3,  
SELB_2,  
SELB_1,  
SELB_0  
Clock select pins for Bank B outputs. See Control Input  
Pulldown Function Table. LVCMOS/LVTTL interface levels.  
See Table 3C.  
Input  
30, 31  
nQB1, QB  
nCLK9  
CLK9  
Output  
Input  
Input  
Input  
Input  
Input  
Input  
Clock outputs. LVDS interface levels.  
Pullup/  
35  
Inverting differential clock input. VCC/2 default when left floating.  
Pulldown  
36  
Pullup  
Non-inverting differential clock input.  
Pullup/  
Pulldown  
37  
nCLK10  
CLK10  
nCLK11  
CLK11  
Inverting differential clock input. VCC/2 default when left floating.  
Non-inverting differential clock input.  
38  
Pullup  
Pullup/  
Pulldown  
40  
Inverting differential clock input. VCC/2 default when left floating.  
41  
Pullup  
Non-inverting differential clock input.  
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
IDT™ / ICS™ 3.3V, 2.5V LVPECL MULTIPLEXER  
2
ICS853S202AKI REV. A JANUARY 25, 2007  
1234567...20

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