Datasheet > 853S202AYI

853S202AYI

更新时间： 2023-01-03 10:01:58

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
20页	559K
描述
Clock Driver

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

853S202AYI 数据手册

ICS853S202I

12:2, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL MULTIPLEXER

PRELIMINARY

TABLE 4D. DIFFERENTIAL DC CHARACTERISTICS, V_CC= 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = -40°C TO 85°C

Symbol Parameter

I_IHInput High Current

Test Conditions

Minimum Typical Maximum Units

CLK0:CLK11

_CC= V_IN= 3.465V or 2.625V

V_CC= 3.465V or 2.625V,

150

µA

nCLK0:nCLK11

CLK0:CLK11

-5

µA

_IN= 0V

_CC= 3.465V or 2.625V,

_IN= 0V

I_IL

Input Low Current

nCLK0:nCLK11

-150

V_PP

Peak-to-Peak Input Voltage

0.15

1.3

Common Mode Input Voltage;

NOTE 1, 2

V_CMR

GND + 0.5

V_CC- 0.85

NOTE 1: Common mode voltage is defined as V_IH.

NOTE 2: For single ended applications, the maximum input voltage for CLKx, nCLKx is V_CC+ 0.3V.

TABLE 4E. LVPECL DC CHARACTERISTICS, V_CC= 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum

V_CC- 1.4

V_CC- 2.0

0.6

Typical

Maximum Units

V_OH

Output High Voltage Voltage; NOTE 1

V_CC- 0.9

V_CC- 1.7

1.0

V_OL

Output Low Voltage; NOTE 1

V_SWING

Peak-to-Peak Output Voltage Swing

NOTE 1: Outputs terminated with 50Ω to V_CC- 2V.

TABLE 5A. AC CHARACTERISTICS, V_CC= 3.3V 5ꢀ TA = -40°C TO 85°C

Symbol

Parameter

Test Conditions

Minimum Typical Maximum Units

f_MAX

Output Frequency

GHz

Propagation Delay, Low to High;

NOTE 1

Propagation Delay, High to Low;

NOTE 1

tp_LH

tp_HL

690

tsk(o)

tsk(i)

Output Skew; NOTE 2, 3

Input Skew; NOTE 3

TBD

tsk(pp)

Part-to-Part Skew; NOTE 3, 4

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter section,

NOTE 5

155.52MHz,

Integration Range:

12kHz - 20MHz

tjit

0.13

t_R/ t_F

odc

Output Rise/Fall Time

Output Duty Cycle

20ꢀ to 80ꢀ

120

ꢀ

MUX_ISOLATIONMUX Isolation

f_OUT< 1.2GHz

All parameters measured at 500MHz, unless noted otherwise.

NOTE 1: Measured from V_CC/2 of the input to V_CC/2 of the output.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_CC/2.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and

with equal load conditions. Using the same type of input on each device, the output is measured at V_CC/2.

NOTE 5: Driving only one input clock.

IDT^™/ ICS^™3.3V, 2.5V LVPECL MULTIPLEXER

ICS853S202AKI REV. A JANUARY 25, 2007

1...3 4 567 8 9...20

下载PDF

与853S202AYI相关器件

型号	品牌	描述	获取价格	数据表
853S202I	RENESAS	12:2 Differential-to-LVPECL Clock Multiplexer	获取价格
853S314AFI	IDT	Low Skew Clock Driver, 853S Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 5.30 M	获取价格
853S314AFILF	IDT	Low Skew Clock Driver, 853S Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 5.30 M	获取价格
853S314AFILFT	IDT	SSOP-20, Reel	获取价格
853S314AFIT	IDT	Low Skew Clock Driver, 853S Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 5.30 M	获取价格
853S314AGI	IDT	Low Skew Clock Driver, 853S Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 4.40 M	获取价格