Datasheet > 853S057I

853S057I

更新时间： 2023-12-20 18:44:21

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
16页	691K
描述
4:1 Differential-to-3.3V, 2.5V LVPECL / ECL Clock Multiplexer

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853S057I 数据手册

853S057 Datasheet

4:1, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL CLOCK DATA MULTIPLEXER

Application Information

Wiring the Differential Input to Accept Single-Ended Levels

Figure 1 shows how the differential input can be wired to accept

single-ended levels. The reference voltage V_REF = V_CC/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio of

R1 and R2 might need to be adjusted to position the V_REF in the

center of the input voltage swing. For example, if the input clock

swing is only 2.5V and V_CC= 3.3V, V_REF should be 1.25V and

V_CC

R2/R1 = 0.609.

Single Ended Clock Input

CLKx

V_REF

nCLKx

0.1u

Figure 1. Single-Ended Signal Driving Differential Input

Recommendations for Unused Input Pins

Inputs:

CLK/nCLK Inputs

For applications not requiring the use of the differential input, a 1k

resistor should be tied from nCLK to V_CC

Single-ended LVPECL Control Pins

All control pins have internal pulldowns; additional resistance is not

required but can be added for additional protection. A 1k resistor

can be used.

853S057AGI AUGUST 13, 2021

1...4 5 678 9 10...16

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型号	品牌	描述	获取价格	数据表
853S111AI	IDT	Differential-to-LVPECL/ECL Fanout Buffer	获取价格
853S111AI	RENESAS	Low Skew,1-to-10 Differential-to-LVPECL/ECL Fanout Buffer	获取价格
853S111AYILF	IDT	Differential-to-LVPECL/ECL Fanout Buffer	获取价格
853S111AYILFT	IDT	Differential-to-LVPECL/ECL Fanout Buffer	获取价格
853S111B	IDT	Low Skew, 1-to-10, Differential-to-2.5V, 3.3V LVPECL/ECL Fanout Buffer	获取价格
853S111B_16	IDT	Low Skew, 1-to-10, Differential-to-2.5V, 3.3V LVPECL/ECL Fanout Buffer	获取价格