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853S057I PDF预览

853S057I

更新时间: 2023-12-20 18:44:21
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
16页 691K
描述
4:1 Differential-to-3.3V, 2.5V LVPECL / ECL Clock Multiplexer

853S057I 数据手册

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853S057 Datasheet  
4:1, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL CLOCK DATA MULTIPLEXER  
Clock Input Interface  
The CLK/nCLK accepts LVPECL, LVDS, CML, SSTL and other  
differential signals. Both VSWING and VOH must meet the VPP and  
driver types. The input interfaces suggested here are examples only.  
If the driver is from another vendor, use their termination  
recommendation. Please consult with the vendor of the driver  
component to confirm the driver termination requirements.  
VCMR input requirements. Figures 2A to2E show interface examples  
for the HiPerClockS CLK /nCLK input driven by the most common  
Figure 2A. HiPerClockS CLK/nCLK Input  
Driven by a CML Driver  
Figure 2B. HiPerClockS CLK/nCLK Input  
Driven by a Built-In Pullup CML Driver  
3.3V  
3.3V  
3.3V  
3.3V  
R3  
125  
R4  
125  
3.3V  
Zo = 50  
Zo = 50  
Zo = 50  
CLK  
CLK  
R1  
100  
nCLK  
nCLK  
Zo = 50  
Differential  
Input  
LVPECL  
Differential  
LVDS  
R1  
84  
R2  
84  
Input  
Figure 2C. HiPerClockS CLK/nCLK Input  
Driven by a 3.3V LVPECL Driver  
Figure 2D. HiPerClockS CLK/nCLK Input Driven by  
a 3.3V LVDS Driver  
2.5V  
3.3V  
2.5V  
R3  
R4  
120  
120  
Zo = 60  
Zo = 60  
CLK  
nCLK  
Differential  
Input  
SSTL  
R1  
120  
R2  
120  
Figure 2E. HiPerClockS CLK/nCLK Input  
Driven by an SSTL Driver  
853S057AGI AUGUST 13, 2021  
8
©2021 Renesas Electronics Corporation  

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