Datasheet > 844256BGI

844256BGI

更新时间： 2023-05-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
16页	346K
描述
Clock Generator, PDSO24

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844256BGI 数据手册

ICS844256I

FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER

LVCMOS TO XTAL INTERFACE

The XTAL_IN input can accept a single-ended LVCMOS signal

through an AC couple capacitor. A general interface diagram is

shown in Figure 3. The XTAL_OUT pin can be left floating. The

input edge rate can be as slow as 10ns. For LVCMOS inputs, it

is recommended that the amplitude be reduced from full swing

to half swing in order to prevent signal interference with the

power rail and to reduce noise. This configuration requires that

the output impedance of the driver (Ro) plus the series

resistance (Rs) equals the transmission line impedance. In

addition, matched termination at the crystal input will attenuate

the signal in half. This can be done in one of two ways. First,

R1 and R2 in parallel should equal the transmission line

impedance. For most 50Ω applications, R1 and R2 can be 100Ω.

This can also be accomplished by removing R1 and making R2

50Ω.

V_DD

VCC

V_DD

VCC

.1uf

Zo = 50

XTAL_IN

Zo = Ro + Rs

XTAL_OU T

FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE

3.3V, 2.5V LVDS DRIVER TERMINATION

A general LVDS interface is shown in Figure 4. In a 100Ω

differential transmission line environment, LVDS drivers

require a matched load termination of 100Ω across near

the receiver input.

2.5V or 3.3V

VDD

LVDS_Driv er

100

100 Ohm Differential Transmission Line

FIGURE 4. TYPICAL LVDS DRIVER TERMINATION

IDT^™/ ICS^™LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER

ICS844256BGI REV. A DECEMBER 21, 2007

Reference Document: JEDEC Publication 95, MO-153

1...7 8 91011 12 13...16

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