Datasheet > 844256CK-24T

844256CK-24T

更新时间： 2024-02-12 08:20:20

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
16页	1376K
描述
Clock Generator

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技术参数
数据手册

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844256CK-24T 技术参数

生命周期：	Active	Reach Compliance Code：	compliant
风险等级：	5.8	Base Number Matches：	1

844256CK-24T 数据手册

PRELIMINARY

FEMTOCLOCKS™ CRYSTAL-TO-LVDS

FREQUENCY SYNTHESIZER

ICS844256-24

GENERAL DESCRIPTION

FEATURES

The ICS844256-24 is a 6 differential output LVDS

• Six 3.3V differential LVDS output pairs

ICS

HiPerClockS™

Synthesizer designed to generate reference clocks

for SPI-4.2 and XAUI/XGMII 10Gb Ethernet inter-

faces and is a member of the HiPerClocks™family of

high performance clock solutions from IDT. Using a

• Using a 31.25MHz crystal, the two output banks can be

independently set for 390.625MHz, 312.5MHz, 195.3125MHz

or 156.25MHz

• Crystal oscillator interface

• VCO: 1562.5MHz

31.25MHz, 18pF parallel resonant crystal, the following fre-

quencies can be generated based on the settings of frequency

select pins: 390.625MHz, 312.5MHz, 195.3125MHz and

156.25MHz.

• RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):

0.62ps (typical)

• Full 3.3V supply mode

The two banks have their own dedicated frequency select pins

and can be independently set for the frequencies mentioned

above.The ICS844256-24, with low phase noise VCO technology,

can achieve 1ps or lower typical rms phase jitter, easily meeting

SPI-4.2 and 10Gb Ethernet jitter requirements. The ICS844256-

24 is packaged in a small 32-pin VFQFN package.

• 0°C to 70°C ambient operating temperature

• Industrial temperature available upon request

• Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

PIN ASSIGNMENT

32 31 30 29 28 27 26 25

V^DDO_A

DIV_SEL_B1

DIV_SEL_B0

DIV_SEL_A1

QA0

nQA0

QA1

ICS844256-24

32-Lead VFQFN

5mm x 5mm x 0.75mm

package body

DIV_SEL_A0

OEB

nQA1

GND

OEA

K Package

Top View

BLOCK DIAGRAM

QB0

V^DD

nQB0

GND

Pullup

OEA

10 11 12 13 14 15 16

Pulldown

Pullup

DIV_SELA[0:1]

PLL_SEL

QA0

÷4 (default)

÷5

÷8

÷16

nQA0

Pulldown

REF_CLK

XTAL_IN

QA1

Phase

Detector

VCO

nQA1

1562.5MHz

OSC

QB0

XTAL_OUT

nXTAL_SEL

÷4

÷8

nQB0

QB1

÷10 (default)

÷16

Pulldown

nQB1

QB2

Feedback Divider

0 = ÷50 (fixed)

nQB2

QB3

nQB3

Pulldown

DIV_SELB[0:1]

OEB

Pulldown:Pullup

Pullup

The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization

and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.

IDT^™/ ICS^™LVDS FREQUENCY SYNTHESIZER

ICS844256CK-24 REV. A MARCH 28, 2007

12 3 4 5 6 7...16

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