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8430DY-111LFT PDF预览

8430DY-111LFT

更新时间: 2024-02-20 09:05:23
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
18页 171K
描述
Clock Driver, 8430 Series, 2 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32

8430DY-111LFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32针数:32
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.54
系列:8430输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G32JESD-609代码:e3
长度:7 mm逻辑集成电路类型:CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:2最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):260
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.015 ns
座面最大高度:1.6 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:7 mm
最小 fmax:700 MHzBase Number Matches:1

8430DY-111LFT 数据手册

 浏览型号8430DY-111LFT的Datasheet PDF文件第5页浏览型号8430DY-111LFT的Datasheet PDF文件第6页浏览型号8430DY-111LFT的Datasheet PDF文件第7页浏览型号8430DY-111LFT的Datasheet PDF文件第9页浏览型号8430DY-111LFT的Datasheet PDF文件第10页浏览型号8430DY-111LFT的Datasheet PDF文件第11页 
700MHz, Low Jitter, Differential-to-  
3.3V LVPECL Frequency Synthesizer  
ICS8430-111  
PRELIMINARY DATA SHEET  
PARAMETER MEASUREMENT INFORMATION  
2V  
VCC  
SCOPE  
VCC,  
VCCA  
Qx  
,
nCLK  
VCCO  
VPP  
VCMR  
Cross Points  
LVPECL  
nQx  
CLK  
VEE  
VEE  
-1.3V 0.165V  
3.3V OUTPUT LOAD AC TEST CIRCUIT  
DIFFERENTIAL INPUT LEVEL  
VOH  
VREF  
nFOUTx  
FOUTx  
VOL  
nFOUTy  
1σ contains 68.26% of all measurements  
2σ contains 95.4% of all measurements  
3σ contains 99.73% of all measurements  
4σ contains 99.99366% of all measurements  
6σ contains (100-1.973x10-7)% of all measurements  
FOUTy  
tsk(o)  
Histogram  
Reference Point  
(Trigger Edge)  
Mean Period  
(First edge after trigger)  
OUTPUT SKEW  
PERIOD JITTER  
nFOUTx  
FOUTx  
nFOUTx  
FOUTx  
tPW  
tPERIOD  
tcycle n  
tcycle n+1  
tjit(cc) = tcycle n – tcycle n+1  
tPW  
1000 Cycles  
odc =  
x 100%  
tPERIOD  
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD  
CYCLE-TO-CYCLE JITTER  
80%  
tF  
80%  
VSWING  
Clock  
20%  
20%  
Outputs  
tR  
OUTPUT RISE/FALL TIME  
ICS8430DY-111 REVISION F JUNE 22, 2009  
8
©2009 Integrated Device Technology, Inc.  

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