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841S012DKILF

更新时间: 2024-02-10 07:25:55
品牌 Logo 应用领域
艾迪悌 - IDT 晶体时钟发生器微控制器和处理器外围集成电路PC
页数 文件大小 规格书
22页 187K
描述
Crystal-to-0.7V Differential HCSL/LVCMOS Frequency Synthesizer

841S012DKILF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:VFQFPN
包装说明:HVQCCN, LCC56,.31SQ,20针数:56
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.29
JESD-30 代码:S-XQCC-N56JESD-609代码:e3
长度:8 mm湿度敏感等级:3
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C最大输出时钟频率:250 MHz
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC56,.31SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):260
电源:3.3 V主时钟/晶体标称频率:25 MHz
认证状态:Not Qualified座面最大高度:1 mm
子类别:Clock Generators最大压摆率:300 mA
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:8 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

841S012DKILF 数据手册

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ICS841S012DI Data Sheet  
CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER  
TABLE 1. PIN DESCRIPTIONS  
Number  
1
Name  
VDD_REFOUT  
VDD  
Type  
Description  
Poꢁer  
Poꢁer  
Output supply pin for REF_OUT.  
Core supply pins.  
7, 14, 28, 29  
2,  
3
REF_OUT0,  
REF_OUT1  
Single-ended LVCMOS/LVTTL reference clock outputs.  
23Ω typical output impedance.  
Output  
4, 5, 15, 27,  
35, 36, 40, 46,  
50, 54  
GND  
Poꢁer  
Poꢁer supply ground.  
6
REF_IN  
Input Pulldoꢁn Single-ended LVCMOS/LVTTL reference clock input.  
Reference select pin. When HIGH selects REF_IN. When LOW,  
Input Pulldoꢁn  
8
REF_SEL  
selects crystal. LVCMOS/LVTTL interface levels. See Table 3E.  
9,  
10  
XTAL_IN,  
XTAL_OUT  
Crystal oscillator interface. XTAL_OUT is the output. XTAL_IN is the input.  
External tuning capacitor must be used for proper operation.  
Input  
When HIGH bypasses PLL. When LOW, selects PLL.  
LVCMOS/LVTTL interface levels. See Table 3J.  
Active HIGH REF_OUT enables/disables pin.  
LVCMOS/LVTTL interface levels. See Table 3H.  
11  
12  
BYPASS  
REF_OE  
Input Pulldoꢁn  
Input Pulldoꢁn  
Active LOW Master Reset. When logic LOW, the internal dividers are reset  
and the outputs are in high impedance (HI-Z). When logic HIGH, the  
internal dividers and the outputs are enabled.  
LVCMOS/LVTTL interface levels. See Table 3I.  
13  
nMR  
Input  
Input  
Pullup  
Pullup  
16,  
17  
SSC1,  
SSC0  
SSC control pin. LVCMOS/LVTTL interface levels. See Table 3D.  
18,  
19,  
20  
21,  
22,  
23  
F_SELB2,  
F_SELB1,  
F_SELB0  
F_SELC2,  
F_SELC1,  
F_SELC0  
F_SELA1,  
F_SELA0  
Frequency select pins for QBx outputs. See Table 3B.  
LVCMOS/LVTTL interface levels.  
Input Pulldoꢁn  
Frequency select pins for QC output. See Table 3C.  
LVCMOS/LVTTL interface levels.  
Input Pulldoꢁn  
Input Pulldoꢁn  
24,  
25  
Frequency select pins for QAx/nQAx outputs. See Table 3A.  
LVCMOS/LVTTL interface levels.  
Output enable pin for Bank A outputs. See Table 3F. LVCMOS/LVTTL  
interface levels.  
26  
QA_OE  
Input  
Pullup  
Pullup  
30, 31  
32, 33  
nQA1, QA1  
nQA0, QA0  
Output  
Differential Bank A clock outputs. HCSL interface levels.  
External fixed precision resistor (475Ω) from this pin to ground provides a  
reference current used for differential current-mode QAx/nQAx clock  
outputs.  
34  
IREF  
Output  
37, 38  
39  
VDDA  
Poꢁer  
Input  
Analog supply pin.  
Output enable pin for Bank B and Bank C outputs.  
LVCMOS/LVTTL Interface levels. See Table 3G.  
Single-ended Bank C clock output. LVCMOS/LVTTL interface levels.  
18Ω typical output impedance.  
QBC_OE  
41  
QC  
Output  
42  
VDDOC  
VDDOB  
Poꢁer  
Poꢁer  
Output supply pin for QC LVCMOS output.  
43, 48, 52, 56  
Output supply pins for QBx LVCMOS outputs.  
44, 45,  
47, 49,  
51, 53, 55  
QB0, QB1,  
QB2, QB3,  
QB4, QB5, QB6  
Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels.  
18Ω typical output impedance.  
Output  
NOTE: Pullup and Pulldoꢁn refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
ICS841S012DKI REVISION A JULY 20, 2009  
3
©2009 Integrated Device Technology, Inc.  

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