ICS841S012DI Data Sheet
CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
1
Name
VDD_REFOUT
VDD
Type
Description
Poꢁer
Poꢁer
Output supply pin for REF_OUT.
Core supply pins.
7, 14, 28, 29
2,
3
REF_OUT0,
REF_OUT1
Single-ended LVCMOS/LVTTL reference clock outputs.
23Ω typical output impedance.
Output
4, 5, 15, 27,
35, 36, 40, 46,
50, 54
GND
Poꢁer
Poꢁer supply ground.
6
REF_IN
Input Pulldoꢁn Single-ended LVCMOS/LVTTL reference clock input.
Reference select pin. When HIGH selects REF_IN. When LOW,
Input Pulldoꢁn
8
REF_SEL
selects crystal. LVCMOS/LVTTL interface levels. See Table 3E.
9,
10
XTAL_IN,
XTAL_OUT
Crystal oscillator interface. XTAL_OUT is the output. XTAL_IN is the input.
External tuning capacitor must be used for proper operation.
Input
When HIGH bypasses PLL. When LOW, selects PLL.
LVCMOS/LVTTL interface levels. See Table 3J.
Active HIGH REF_OUT enables/disables pin.
LVCMOS/LVTTL interface levels. See Table 3H.
11
12
BYPASS
REF_OE
Input Pulldoꢁn
Input Pulldoꢁn
Active LOW Master Reset. When logic LOW, the internal dividers are reset
and the outputs are in high impedance (HI-Z). When logic HIGH, the
internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels. See Table 3I.
13
nMR
Input
Input
Pullup
Pullup
16,
17
SSC1,
SSC0
SSC control pin. LVCMOS/LVTTL interface levels. See Table 3D.
18,
19,
20
21,
22,
23
F_SELB2,
F_SELB1,
F_SELB0
F_SELC2,
F_SELC1,
F_SELC0
F_SELA1,
F_SELA0
Frequency select pins for QBx outputs. See Table 3B.
LVCMOS/LVTTL interface levels.
Input Pulldoꢁn
Frequency select pins for QC output. See Table 3C.
LVCMOS/LVTTL interface levels.
Input Pulldoꢁn
Input Pulldoꢁn
24,
25
Frequency select pins for QAx/nQAx outputs. See Table 3A.
LVCMOS/LVTTL interface levels.
Output enable pin for Bank A outputs. See Table 3F. LVCMOS/LVTTL
interface levels.
26
QA_OE
Input
Pullup
Pullup
30, 31
32, 33
nQA1, QA1
nQA0, QA0
Output
Differential Bank A clock outputs. HCSL interface levels.
External fixed precision resistor (475Ω) from this pin to ground provides a
reference current used for differential current-mode QAx/nQAx clock
outputs.
34
IREF
Output
37, 38
39
VDDA
Poꢁer
Input
Analog supply pin.
Output enable pin for Bank B and Bank C outputs.
LVCMOS/LVTTL Interface levels. See Table 3G.
Single-ended Bank C clock output. LVCMOS/LVTTL interface levels.
18Ω typical output impedance.
QBC_OE
41
QC
Output
42
VDDOC
VDDOB
Poꢁer
Poꢁer
Output supply pin for QC LVCMOS output.
43, 48, 52, 56
Output supply pins for QBx LVCMOS outputs.
44, 45,
47, 49,
51, 53, 55
QB0, QB1,
QB2, QB3,
QB4, QB5, QB6
Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels.
18Ω typical output impedance.
Output
NOTE: Pullup and Pulldoꢁn refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
ICS841S012DKI REVISION A JULY 20, 2009
3
©2009 Integrated Device Technology, Inc.