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840002AG-01T PDF预览

840002AG-01T

更新时间: 2024-11-24 15:45:59
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
13页 514K
描述
Clock Generator, 175MHz, PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, MO-153, TSSOP-16

840002AG-01T 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP16,.25针数:16
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.35
Is Samacsys:NJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:5 mm
湿度敏感等级:1端子数量:16
最高工作温度:85 °C最低工作温度:-30 °C
最大输出时钟频率:175 MHz封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):225电源:2.5/3.3 V
主时钟/晶体标称频率:25 MHz认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Clock Generators
最大压摆率:100 mA最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

840002AG-01T 数据手册

 浏览型号840002AG-01T的Datasheet PDF文件第2页浏览型号840002AG-01T的Datasheet PDF文件第3页浏览型号840002AG-01T的Datasheet PDF文件第4页浏览型号840002AG-01T的Datasheet PDF文件第5页浏览型号840002AG-01T的Datasheet PDF文件第6页浏览型号840002AG-01T的Datasheet PDF文件第7页 
®
ICS840002-01  
FemtoClock , Crystal-to-LVCMOS/LVTTL  
Frequency Synthesizer  
DATA SHEET  
General Description  
Features  
The ICS840002-01 is a two output LVCMOS/LVTTL Synthesizer  
optimized to generate Ethernet reference clock frequencies. Using a  
25MHz 18pF parallel resonant crystal, the following frequencies can  
be generated based on the two frequency select pins (F_SEL[1:0]):  
156.25MHz, 125MHz, and 62.5MHz. The ICS840002-01 uses IDT’s  
3RD generation low phase noise VCO technology and can achieve  
1ps or lower typical random rms phase jitter, easily meeting Ethernet  
jitter requirements. The ICS840002-01 is packaged in a small 16-pin  
TSSOP package.  
Two LVCMOS/LVTTL outputs@ 3.3V,  
17typical output impedance  
Selectable crystal oscillator interface or LVCMOS/LVTTL  
single-ended TEST_CLK  
Output frequency range: 56MHz to 175MHz  
VCO range: 560MHz to 700MHz  
Output skew: 12ps (maximum)  
RMS phase jitter at 156.25MHz, (1.875MHz to 20MHz):  
0.47ps (typical)  
Phase Noise:  
Offset  
Noise Power  
100Hz.................-97.4 dBc/Hz  
1kHz...................-120.2 dBc/Hz  
10kHz.................-127.6 dBc/Hz  
100kHz...............-126.1 dBc/Hz  
Full 3.3V or mixed 3.3V core/2.5V output supply modes  
-30°C to 85°C ambient operating temperature  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
Frequency Select Function Table  
Inputs  
F_SEL1  
F_SEL0  
M Divider Value  
N Divider Value  
Output Frequency (25MHz Ref.)  
0
0
1
1
0
1
0
1
25  
25  
25  
25  
4
5
156.25  
125  
10  
5
62.5  
125  
Pin Assignment  
Block Diagram  
F_SEL1  
GND  
GND  
Q0  
F_SEL0  
nXTAL_SEL  
TEST_CLK  
OE  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
Pullup  
OE  
2
Pullup:Pullup  
F_SEL1:0  
MR  
Q1  
Pulldown  
nPLL_SEL  
nPLL_SEL  
VDDA  
VDDO  
10 XTAL_IN  
XTAL_OUT  
Pulldown  
nXTAL_SEL  
9
VDD  
XTAL_IN  
ICS840002-01  
F_SEL1:0  
N
0
Q0  
Q1  
OSC  
1
0
16-Lead TSSOP  
4.4mm x 5.0mm x 0.925mm  
package body  
XTAL_OUT  
TEST_CLK  
0 0 ÷4  
0 1 ÷5  
1 0 ÷10  
1 1 ÷5  
Phase  
Detector  
Pulldown  
1
VCO  
G Package  
Top View  
M = ÷25 (fixed)  
Pulldown  
MR  
ICS840002AG-01 REVISION D SEPTEMBER 28, 2012  
1
©2012 Integrated Device Technology, Inc.  

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