Low Skew, 1-to18
ICS83940DI
LVPECL-to-LVCMOS/LVTTL Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017 (83940DKILF)
DATA SHEET
General Description
Features
TheICS83940DI isalow skew, 1-to-18 LVPECL- to-LVCMOS/LVTTL
Fanout Buffer. The ICS83940DI has two selectable clock inputs. The
PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels.
The LVCMOS_CLK can accept LVCMOS or LVTTL input levels. The
low impedance LVCMOS/LVTTL outputs are designed to drive 50
series or parallel terminated transmission lines.
• Eighteen LVCMOS/LVTTL outputs
• Selectable LVCMOS_CLK or LVPECL clock inputs
• PCLK, nPCLK pair can accept the following differential input
levels: LVPECL, CML, SSTL
• LVCMOS_CLK supports the following input types: LVCMOS or
LVTTL
The ICS83940DI is characterized at full 3.3V and 2.5V or mixed 3.3V
core, 2.5V output operating supply modes. Guaranteed output and
part-to-part skew characteristics make the ICS83940DI ideal for
those clock distribution applications demanding well defined
performance and repeatability.
• Maximum output frequency: 250MHz
• Output skew: 150ps (maximum)
• Part-to-part skew: 750ps (maximum)
• Operating supply modes:
• Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
Block Diagram
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
Pulldown
CLK_SEL
• For functional replacement part for 83940DKILF use 87016i
Pulldown
PCLK
0
Pullup/Pulldown
nPCLK
18
Q0:Q17
Pulldown
LVCMOS_CLK
1
Pin Assignments
32 31 30 29 28 27 26 25
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
GND
Q6
Q7
Q8
24
23
22
21
20
GND
GND
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
Q6
GND
Q7
LVCMOS_CLK
LVCMOS_CLK
CLK_SEL
PCLK
Q8
VDD
Q9
CLK_SEL
PCLK
VDD
Q9
ICS83940DI
ICS83940DI
nPCLK
nPCLK
VDD
Q10
Q11
GND
Q10
Q11
GND
19
18
17
VDD
VDDO
VDDO
9
10 11 12 13 14 15 16
9
10 11 12 13 14 15 16
32 Lead VFQFN
32-Lead LQFP
5mm x 5mm x 0.925mm package body
7mm x 7mm x 1.4mm package body
Y Package
Top View
K Package
Top View
ICS83940DYI REVISION C May 19, 2016
1
©2016 Integrated Device Technology, Inc.