Datasheet > 82C55

82C55

更新时间： 2024-11-22 22:23:51

品牌	Logo	应用领域
英特尔 - INTEL		/
页数	文件大小	规格书
23页	324K
描述
CHMOS PROGRAMMABLE PERIPHERAL INTERFACE

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82C55 数据手册

82C55A

CHMOS PROGRAMMABLE PERIPHERAL INTERFACE

Compatible with all Intel and Most

Other Microprocessors

Control Word Read-Back Capability

Direct Bit Set/Reset Capability

High Speed, ‘‘Zero Wait State’’

Operation with 8 MHz 8086/88 and

80186/188

2.5 mA DC Drive Capability on all I/O

Port Outputs

Available in 40-Pin DIP and 44-Pin PLCC

24 Programmable I/O Pins

Low Power CHMOS

Available in EXPRESS

Ð Standard Temperature Range

Ð Extended Temperature Range

Completely TTL Compatible

The Intel 82C55A is a high-performance, CHMOS version of the industry standard 8255A general purpose

programmable I/O device which is designed for use with all Intel and most other microprocessors. It provides

24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation.

The 82C55A is pin compatible with the NMOS 8255A and 8255A-5.

In MODE 0, each group of 12 I/O pins may be programmed in sets of 4 and 8 to be inputs or outputs. In

MODE 1, each group may be programmed to have 8 lines of input or output. 3 of the remaining 4 pins are used

for handshaking and interrupt control signals. MODE 2 is a strobed bi-directional bus configuration.

The 82C55A is fabricated on Intel’s advanced CHMOS III technology which provides low power consumption

with performance equal to or greater than the equivalent NMOS product. The 82C55A is available in 40-pin

DIP and 44-pin plastic leaded chip carrier (PLCC) packages.

231256–31

231256–1

Figure 1. 82C55A Block Diagram

231256–2

Figure 2. 82C55A Pinout

Diagrams are for pin reference only. Package

sizes are not to scale.

October 1995

Order Number: 231256-004

12 3 4 5 6 7...23

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