82077AA
ters. This interface can be switched between PC AT,
Model 30, or PS/2 normal modes. The PS/2 register
sets are a superset of the registers found in a PC-
AT.
1.1 Oscillator
2.1 Status, Data and Control Registers
The base address range is supplied via the CS pin.
For PC-AT or PS/2 designs this would be 3F0 Hex
to 3F7 Hex.
290166–3
Figure 1-2. Crystal Oscillator Circuit
A2 A1 A0
Register
The 24 MHz clock can be supplied either by a crystal
or a MOS level square wave. All internal timings are
referenced to this clock or a scaled count which is
data rate dependent.
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
1
1
1
0
1
0
1
0
0
1
0
1
1
R
R
Status Register A
Status Register B
SRA
SRB
DOR
TDR
MSR
DSR
FIFO
R/W Digital Output Register
R/W Tape Drive Register
R
Main Status Register
The crystal oscillator must be allowed to run for
10 ms after VCC has reached 4.5V or exiting the
POWERDOWN mode to guarantee that it is stable.
W
Data Rate Select Register
R/W Data (FIFO)
Reserved
Crystal Specifications
R
Digital Input Register
DIR
W
Configuration Control Register CCR
g
24 MHz 0.1%
Frequency:
Mode:
Parallel Resonant
Fundamental Mode
2.1.1a STATUS REGISTER A (SRA, PS/2 MODE)
Series Resistance: Less than 40X
This register is read-only and monitors the state of
the interrupt pin and several disk interface pins. This
register is part of the register set, and is not accessi-
ble in PC-AT mode.
Shunt Capacitance: Less than 5 pF
1.2 Perpendicular Recording Mode
7
6*
5
4*
3
2*
1*
0
An added capability of the 82077AA is the ability to
interface directly to perpendicular recording floppy
drives. Perpendicular recording differs from the tradi-
tional longitudinal method by orienting the magnetic
bits vertically. This scheme packs in more data bits
for the same area.
INT
PENDING
DRV2 STEP TRK0 HDSEL INDX WP DIR
The INT PENDING bit is used by software to monitor
the state of the 82077AA INTERRUPT pin. The bits
marked with a ‘‘*’’ reflect the state of drive signals
on the cable and are independent of the state of the
INVERT pin.
The 82077AA with perpendicular recording drives
can read standard 3.5 floppies as well as read and
×
write perpendicular media. Some manufacturers of-
fer drives that can read and write standard and per-
pendicular media in a perpendicular media drive.
As a read-only register, there is no default value as-
sociated with a reset other than some drive bits will
change with a reset. The INT PENDING, STEP,
HDSEL, and DIR bits will be low after reset.
A single command puts the 82077AA into perpen-
dicular mode. All other commands operate as they
normally do. The perpendicular mode requires the
1 Mbps data rate of the 82077AA. At this data rate,
the FIFO eases the host interface bottleneck due to
the speed of data transfer to or from the disk.
2.1.1b STATUS REGISTER A (SRA, MODEL 30
MODE)
7
6
5
4
3
2
1
0
INT
PENDING
STEP
F/F
2.0 MICROPROCESSOR INTERFACE
DRQ
TRKO HDSEL INDEX WP DIR
The interface consists of the standard asynchronous
signals: RD, WR, CS, A0–A2, INT, DMA control and
a data bus. The address lines select between config-
uration registers, the FIFO and control/status regis-
This register has the following changes in PS/2
Model 30 Mode. Disk interface pins (Bits 0, 1, 2, 3, &
4) are inverted from PS/2 Mode. The DRQ bit
8
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