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82093AA

更新时间： 2024-01-05 21:58:45
品牌 Logo 应用领域
英特尔 - INTEL 中断控制器
页数 文件大小 规格书
20页 179K
描述
I/O ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (IOAPIC)

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82093AA 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：QFP,针数：64
Reach Compliance Code：unknown风险等级：5.83
外部数据总线宽度：8JESD-30 代码：R-PQFP-G64
长度：20 mm外部中断装置数量：24
端子数量：64封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装形状：RECTANGULAR
封装形式：FLATPACK认证状态：Not Qualified
座面最大高度：3.4 mm最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：YES技术：MOS
端子形式：GULL WING端子节距：1 mm
端子位置：QUAD宽度：14 mm
uPs/uCs/外围集成电路类型：INTERRUPT CONTROLLER, MULTIPROCESSORBase Number Matches：1

82093AA 数据手册

 浏览型号82093AA的Datasheet PDF文件第2页浏览型号82093AA的Datasheet PDF文件第3页浏览型号82093AA的Datasheet PDF文件第4页浏览型号82093AA的Datasheet PDF文件第5页浏览型号82093AA的Datasheet PDF文件第6页浏览型号82093AA的Datasheet PDF文件第7页 
PRELIMINARY  
E
82093AA I/O ADVANCED  
PROGRAMMABLE INTERRUPT  
CONTROLLER (IOAPIC)  
¾
¾
3 General Purpose Interrupts  
Provides Multiprocessor Interrupt  
Management  
Independently Programmable for  
Edge/Level Sensitivity Interrupts  
Each Interrupt Can Be Programmed  
to Respond to Active High or Low  
Inputs  
¾
Dynamic Interrupt Distribution-  
¾
Routing Interrupt to the Lowest  
Priority Processor  
Software Programmable Control of  
Interrupt Inputs  
Off Loads Interrupt Related Traffic  
From the Memory Bus  
¾
¾
X-Bus Interface  
¾
¾
¾
CS For Flexible Decode of the  
IOAPIC Device.  
Index Register Interface for  
Optimum Memory Usage  
Registers are 32-Bit Wide to Match  
the PCI to Host Bridge Architecture  
24 Programmable Interrupts  
¾
¾
¾
¾
¾
13 ISA Interrupts Supported  
4 PCI Interrupts  
1 Interrupt/SMI# Rerouting  
2 Motherboard Interrupts  
1 Interrupt Used for INTR Input  
Package 64-Pin PQFP  
The 82093AA I/O Advanced Programmable Interrupt Controller (IOAPIC) provides multi-processor interrupt  
management and incorporates both static and dynamic symmetric interrupt distribution across all processors. In  
systems with multiple I/O subsystems, each subsystem can have its own set of interrupts. Each interrupt pin is  
individually programmable as either edge or level triggered. The interrupt vector and interrupt steering  
information can be specified per interrupt. An indirect register accessing scheme optimizes the memory space  
needed to access the IOAPIC’s internal registers. To increase system flexibility when assigning memory space  
usage, the The IOAPIC’s 2-register memory space is re-locatable.  
D[7:0]  
D/I#  
A[1:0]  
RD#  
WR#  
APIC  
Bus  
Interface  
APCID[1:0]  
APCICLK  
System  
Bus  
CS#  
Interface  
APCID[1:0]  
APCICLK  
APCICLK  
APCIREQ#  
APICACK1#  
APICACK2#  
Interrupt  
Controller  
Clock  
And  
Reset  
RESET  
CLK  
Test  
TESTIN#  
IOA_BLK  
Figure 1. IOAPIC Simplified Block Diagram  
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property  
rights is granted by this document or by the sale of Intel products. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no  
liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to  
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in  
medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. The  
82093AA IOAPIC may contain design defects or errors known as errata. Current characterized errata are available on request. Third-party brands and names are  
the property of their respective owners.  
© INTEL CORPORATION 1996  
May 1996  
Order Number: 290566-001  
1234567...20

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