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82093AA

更新时间： 2024-02-17 08:03:40
品牌 Logo 应用领域
英特尔 - INTEL 中断控制器
页数 文件大小 规格书
20页 179K
描述
I/O ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (IOAPIC)

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中文翻译

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82093AA 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：QFP,针数：64
Reach Compliance Code：unknown风险等级：5.83
外部数据总线宽度：8JESD-30 代码：R-PQFP-G64
长度：20 mm外部中断装置数量：24
端子数量：64封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装形状：RECTANGULAR
封装形式：FLATPACK认证状态：Not Qualified
座面最大高度：3.4 mm最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：YES技术：MOS
端子形式：GULL WING端子节距：1 mm
端子位置：QUAD宽度：14 mm
uPs/uCs/外围集成电路类型：INTERRUPT CONTROLLER, MULTIPROCESSORBase Number Matches：1

82093AA 数据手册

 浏览型号82093AA的Datasheet PDF文件第3页浏览型号82093AA的Datasheet PDF文件第4页浏览型号82093AA的Datasheet PDF文件第5页浏览型号82093AA的Datasheet PDF文件第7页浏览型号82093AA的Datasheet PDF文件第8页浏览型号82093AA的Datasheet PDF文件第9页 
82093AA (IOAPIC)  
E
Signal Name  
Type  
Description  
APICREQ#  
O
APIC REQUEST: APICREQ# is asserted prior to the APIC sending an  
interrupt message over the APIC data bus. This is the request part of a  
handshake that insures system level buffer coherency prior to sending an  
interrupt over the APIC bus. This signal is tri-stated during reset. This signal  
has an internal pull-up resistor.  
APICACK1#  
APICACK2#  
I
I
APIC ACKNOWLEDGE 1: This signal is the acknowledge part of the  
handshake indicating that the APIC can send the interrupt message over the  
APIC bus. This signal is typically connected to the PIIX3.  
APIC ACKNOWLEDGE 2: This signal is the second half of the acknowledge  
handshake indicating that the APIC can send the interrupt message over the  
APIC bus. This signal is typically connected to the host-to-PCI bridge and  
along with APICREQ# and APICACK1# makes up the complete buffer  
coherency protocol cycles. If the system does not have a host-to-PCI bridge,  
this signal can be tied low.  
2.2.  
Clock and Reset Signals  
Signal Name  
Type  
Description  
PCICLK  
I
PCI CLOCK: This signal is used to synchronize and strobe the data buffer  
status signals (APICREQ#, APICACK1#, and APICACK2#). This signal is  
typically connect to the PCI clock.  
RESET  
I
RESET: RESET initializes the IOAPIC’s internal logic and sets the register bits  
to their default value.  
2.3.  
APIC Bus Interface  
Signal Name  
Type  
Description  
APICD[1:0]  
I/OD  
APIC DATA: These signals are used to send and receive data over the APIC  
bus. These signals are tri-stated during reset and must be pulled up to the  
appropriate VCC levels of the CPU.  
APICCLK  
I
APIC CLOCK: The input signal is used to determine when valid data is being  
sent over the APIC bus.  
2.4.  
Interrupt Signals  
Signal Name  
Type  
Description  
INTIN0  
ST  
Interrupt Input 0: This signal is connected to the redirection table entry 0.  
Typically, this signal may be connected to the INTR on the PIIX3 to  
communicate the status of IRQ0 and IRQ13 interrupts. Note that the IRQ0 and  
IRQ13 interrupts are embedded in the PIIX3 and are not available to the rest of  
the system.  
INTIN1  
ST  
Interrupt Input 1: INTIN1 is connected to the redirection table entry 1.  
Typically, this signal will be connected to the keyboard interrupt (IRQ1).  
6
PRELIMINARY  
1...3456789...20

中文翻译

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82093AA 替代型号

型号 品牌 替代类型 描述 数据表
KD82093AA INTEL

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 Interrupt Controller, PCI; ISA Compatible, MOS, PQFP64, PLASTIC, QFP-64

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