Datasheet > 80C52-40R

80C52-40R

更新时间： 2022-12-11 19:08:47

品牌	Logo	应用领域
TEMIC		微控制器
页数	文件大小	规格书
20页	227K
描述
CMOS 0 to 44 MHz Single-chip 8 Bit Microcontroller

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数据手册

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80C52-40R 数据手册

80C32/80C52

MATRA MHS

The capture mode is illustrated in Figure 7.

with the 16 bit value in registers RCAP2L and RCAP2H,

which are preset by software. If EXEN2 = 1, then Timer

2 still does the above, but with the added feature that a

1-to-0 transition at external input T2EX will also trigger

the 16 bit reload and set EXF2.

Figure 7. Timer 2 in Capture Mode.

The auto-reload mode is illustrated in Figure 8.

Figure 8. Timer in Auto-Reload Mode.

In the auto-reload mode there are again two options,

which are selected by bit EXEN2 in T2CON.If

EXEN2 = 0, then when Timer 2 rolls over it does not only

set TF2 but also causes the Timer 2 register to be reloaded

(MSB)

(LSB)

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2

CP/RL2

The baud rate generator mode is selected by : RCLK = 1 and/or TCLK = 1.

Symbol

Position

Name and Significance

TF2

T2CON.7

Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2

will not be set when either RCLK = 1 OR TCLK = 1.

EXF2

T2CON.6

Timer 2 external flag set when either a capture or reload is caused by a negative

transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will

cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by

software.

RCLK

TCLK

T2CON.5

T2CON.4

T2CON.3

Receive clock flag. When set, causes the serial port to use Timer2 overflow pulses for its

receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the

receive clock.

Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for

its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for

the transmit clock.

EXEN2

Timer 2 external enable flag. When set, allows capture or reload to occur as a result of a

negative transition on T2EX if Timer 2 is not being used to clock the serial port.

EXEN2 = 0 causes Timer 2 to ignore events at T2EX.

TR2

T2CON.2

T2CON.1

Start/stop control for Timer 2. A logic 1 starts the timer.

C/T2

Timer or counter select. (Timer 2) 0 = Internal timer (OSC/12)

1 = External event counter (falling edge triggered).

CP/RL2

T2CON.0

Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if

EXEN 2 = 1. When cleared, auto reloads will occur either with Timer 2 overflows or

negative transition at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this

bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.

Rev. E (31/08/95)

1...5 6 789 10 11...20

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