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80523TX300512K PDF预览

80523TX300512K

更新时间: 2024-02-15 19:29:46
品牌 Logo 应用领域
英特尔 - INTEL 时钟外围集成电路
页数 文件大小 规格书
71页 398K
描述
Microprocessor, 32-Bit, 300MHz, CMOS, MINI, CARTRIDGE ASSEMBLY

80523TX300512K 技术参数

生命周期:Active包装说明:,
Reach Compliance Code:compliantECCN代码:3A001.A.3
HTS代码:8542.31.00.01风险等级:5.77
地址总线宽度:36位大小:32
边界扫描:YES最大时钟频率:66.67 MHz
外部数据总线宽度:64格式:FIXED POINT
集成缓存:YESJESD-30 代码:R-XXMA-X
低功率模式:YES封装主体材料:UNSPECIFIED
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
认证状态:Not Qualified速度:300 MHz
最大供电电压:1.72 V最小供电电压:1.48 V
标称供电电压:1.6 V表面贴装:NO
技术:CMOS端子形式:UNSPECIFIED
端子位置:UNSPECIFIEDuPs/uCs/外围集成电路类型:MICROPROCESSOR
Base Number Matches:1

80523TX300512K 数据手册

 浏览型号80523TX300512K的Datasheet PDF文件第4页浏览型号80523TX300512K的Datasheet PDF文件第5页浏览型号80523TX300512K的Datasheet PDF文件第6页浏览型号80523TX300512K的Datasheet PDF文件第8页浏览型号80523TX300512K的Datasheet PDF文件第9页浏览型号80523TX300512K的Datasheet PDF文件第10页 
MOBILE PENTIUM® II PROCESSOR IN MINI-CARTRIDGE PACKAGE  
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ DATASHEET  
1.1 Overview  
1.2  
Terminology  
Performance improved over existing mobile  
processors  
In this document a “#” symbol following a signal  
name indicates that the signal is active low. This  
means that when the signal is asserted (based on  
the name of the signal) it is in an electrical low state.  
Otherwise, signals are driven in an electrical high  
state when they are asserted. In state machine  
diagrams, a signal name in a condition indicates the  
condition of that signal being asserted. If the signal  
name is preceded by a “!” symbol, then it indicates  
the condition of that signal not being asserted. For  
example, the condition “!STPCLK# and HS” is  
equivalent to “the active low signal STPCLK# is  
unasserted (i.e., it is at 2.5V) and the HS condition  
is true.” The symbols “L” and “H” refer respectively  
to electrical low and electrical high signal levels. The  
symbols “0” and “1” refer respectively to logical low  
and logical high signal levels. For example, BD[3:0]  
= “1010” = “HLHL” refers to a hexadecimal “A”, and  
D[3:0]# = “1010” = “LHLH” also refers to a  
Supports the Intel Architecture with Dynamic  
Execution  
Supports the Intel Architecture MMX  
technology  
Integrated Intel Floating-Point Unit  
compatible with the IEEE Std 754  
Integrated primary (L1) instruction and data  
caches  
4-way set associative, 32-byte line size,  
1 line per sector  
16-Kbyte instruction cache and 16-Kbyte  
writeback data cache  
Cacheable range programmable by  
processor programmable registers  
Integrated on-die second level (L2) cache  
4-way set associative, 32-byte line size,  
1 line per sector  
hexadecimal “A.”  
Operates at full core speed  
1.3  
References  
256-Kbyte, ECC protected cache data array  
4-Gbyte cacheable range  
Pentium® II Processor at 233 MHz, 266 MHz, 300  
MHz, and 333 MHz (Order Number 243335)  
Low Power GTL+ system bus interface  
Pentium® II Processor Developer’s Manual  
(Order Number 243502)  
64-bit data bus, 66-MHz operation  
Uniprocessor, two loads only (processor and  
I/O bridge/memory controller)  
CKDM66-M Clock Driver Specification  
(Contact your Intel Field Sales Representative)  
Short trace length and low capacitance  
allows for single ended termination  
CK97 Clock Driver Specification  
(Contact your Intel Field Sales Representative)  
Voltage reduction technology  
Pentium II processor clock control  
Quick Start for low power, low exit latency  
clock “throttling”  
Intel Architecture Software Developer’s Manual  
(Order Number 243193)  
Deep Sleep mode for extremely low power  
dissipation  
Volume I: Basic Architecture  
(Order Number 243190)  
Volume II: Instruction Set Reference  
(Order Number 243191)  
Thermal diode and sensor for measuring  
processor temperature  
Volume III: System Programming Guide  
(Order Number 243192)  
2
INTEL CORPORATION  

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