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80523TX300512K PDF预览

80523TX300512K

更新时间: 2024-02-04 00:42:47
品牌 Logo 应用领域
英特尔 - INTEL 时钟外围集成电路
页数 文件大小 规格书
71页 398K
描述
Microprocessor, 32-Bit, 300MHz, CMOS, MINI, CARTRIDGE ASSEMBLY

80523TX300512K 技术参数

生命周期:Active包装说明:,
Reach Compliance Code:compliantECCN代码:3A001.A.3
HTS代码:8542.31.00.01风险等级:5.77
地址总线宽度:36位大小:32
边界扫描:YES最大时钟频率:66.67 MHz
外部数据总线宽度:64格式:FIXED POINT
集成缓存:YESJESD-30 代码:R-XXMA-X
低功率模式:YES封装主体材料:UNSPECIFIED
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
认证状态:Not Qualified速度:300 MHz
最大供电电压:1.72 V最小供电电压:1.48 V
标称供电电压:1.6 V表面贴装:NO
技术:CMOS端子形式:UNSPECIFIED
端子位置:UNSPECIFIEDuPs/uCs/外围集成电路类型:MICROPROCESSOR
Base Number Matches:1

80523TX300512K 数据手册

 浏览型号80523TX300512K的Datasheet PDF文件第1页浏览型号80523TX300512K的Datasheet PDF文件第2页浏览型号80523TX300512K的Datasheet PDF文件第3页浏览型号80523TX300512K的Datasheet PDF文件第5页浏览型号80523TX300512K的Datasheet PDF文件第6页浏览型号80523TX300512K的Datasheet PDF文件第7页 
MOBILE PENTIUM® II PROCESSOR IN MINI-CARTRIDGE PACKAGE  
AT 400 MHZ, 366 MHZ, 333 MHZ, 300PE MHZ, AND 266PE MHZ DATASHEET  
LIST OF FIGURES  
PAGE  
Figure 1.1 Signal Groups of a Mobile Pentium II  
Mini-cartridge Processor Based System1  
Figure 2.1 Clock Control States............................. 5  
Figure 3.1 Ramp Rate Requirement..................... 13  
Figure 3.2 BCLK Connector to Core Offset.......... 26  
Figure 3.3 Generic Clock Waveform.................... 26  
Figure 3.4 Valid Delay Timings............................ 27  
Figure 3.5 Setup and Hold Timings ..................... 27  
Figure 3.6 Reset and Configuration Timings........ 28  
Figure 3.7 Power-on Reset Timings .................... 28  
Figure 3.8 Test Timings (Boundary Scan) ........... 29  
Figure 3.9 Test Reset Timings............................. 29  
Figure 3.10 Quick Start and Deep Sleep Timing.. 30  
Figure 3.11 Stop Grant, Sleep, and Deep Sleep  
Timing................................................ 31  
Figure 4.1 BCLK Generic Clock Waveform at the  
Processor Core.................................. 33  
Figure 4.2 BCLK Generic Clock Waveform at the  
Processor Connector......................... 34  
Figure 4.3 Low to High, Low Power GTL+ Receiver  
Ringback Tolerance........................... 35  
Figure 4.4 Non-GTL+ Overshoot/Undershoot and  
Ringback............................................ 37  
Figure 5.1 Mini-cartridge Cross Section View ...... 40  
Figure 5.2. Mini-cartridge Assembly, Top Cover (in  
mm)................................................... 41  
Figure 5.3 Mini-cartridge Assembly, Bottom Cover  
and Sides (in mm) ............................. 42  
Figure 5.4 Standoff and Connector Location, Top  
View (in mm)...................................... 43  
Figure 5.5. Mini-cartridge Assembly and Connector  
Keep-out Location, Top View (in mm) 44  
Figure 5.6 Mini-cartridge Cross Section with  
Vertical Dimensions........................... 45  
Figure 8.1 PWRGOOD Relationship at Power-on 59  
iv  
INTEL CORPORATION  

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