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7C1041AV33-10 PDF预览

7C1041AV33-10

更新时间: 2024-11-22 21:53:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
9页 142K
描述
256K x 16 Static RAM

7C1041AV33-10 数据手册

 浏览型号7C1041AV33-10的Datasheet PDF文件第2页浏览型号7C1041AV33-10的Datasheet PDF文件第3页浏览型号7C1041AV33-10的Datasheet PDF文件第4页浏览型号7C1041AV33-10的Datasheet PDF文件第5页浏览型号7C1041AV33-10的Datasheet PDF文件第6页浏览型号7C1041AV33-10的Datasheet PDF文件第7页 
33  
CY7C1041AV33/  
GVT73256A16  
PRELIMINARY  
256K x 16 Static RAM  
Functional Description  
Features  
• Fast access times: 10, 12 ns  
The CY7C1049AV33\GVT73512A8 is organized as a 262,144  
x 16 SRAM using a four-transistor memory cell with a high-per-  
formance, silicon gate, low-power CMOS process. Cypress  
SRAMs are fabricated using double-layer polysilicon, dou-  
ble-layer metal technology.  
• Fast OE access times: 5, 6, and 7 ns  
• Single +3.3V ±0.3V power supply  
• Fully static—no clock or timing strobes necessary  
• All inputs and outputs are TTL-compatible  
• Three state outputs  
• Center power and ground pins for greater noise  
immunity  
• Easy memory expansion with CE and OE options  
• Automatic CE power-down  
This device offers center power and ground pins for improved  
performance and noise immunity. Static design eliminates the  
need for external clocks or timing strobes. For increased sys-  
tem flexibility and eliminating bus contention problems, this de-  
vice offers Chip Enable (CE), separate Byte Enable controls  
(BLE and BHE) and Output Enable (OE) with this organization.  
• High-performance, low power consumption, CMOS  
double-poly, double-metal process  
• Packaged in 44-pin, 400-mil SOJ and 44-pin, 400-mil  
TSOP  
The device offers a low-power standby mode when chip is not  
selected. This allows system designers to meet low standby  
power requirements.  
Functional Block Diagram  
Pin Configuration  
VCC  
VSS  
SOJ/TSOP II  
Top View  
BLE#  
44  
43  
42  
41  
40  
39  
38  
1
2
3
4
5
6
A
A
A
A
0
17  
16  
15  
A
1
DQ1  
DQ8  
DQ9  
DQ16  
A
A0  
2
A
OE  
3
BHE  
BLE  
DQ  
DQ  
DQ  
A
4
CE  
DQ  
DQ  
DQ  
7
1
16  
MEMORY ARRAY  
512 ROWS X 256 X 16  
COLUMNS  
37  
36  
35  
34  
33  
8
2
3
15  
14  
13  
9
10  
11  
12  
13  
DQ  
DQ  
4
V
V
SS  
CC  
V
V
SS  
CC  
32  
31  
30  
29  
28  
27  
DQ  
DQ  
DQ  
DQ  
DQ  
12  
11  
5
6
7
8
DQ  
14  
15  
16  
DQ  
DQ  
NC  
10  
9
WE 17  
18  
A
14  
A
5
19  
26  
25  
A
A
A
A
6
13  
12  
11  
A
20  
21  
22  
A16  
7
POWER  
DOWN  
CE#  
BHE#  
WE#  
COLUMN DECODER  
A
24  
23  
8
9
A
A
10  
OE#  
Selection Guide  
CY7C1049AV33-10/ CY7C1049AV33-12/  
GVT73512A8-10  
GVT73512A8-12  
Maximum Access Time (ns)  
10  
240  
10  
12  
210  
10  
Maximum Operating Current (mA)  
Maximum CMOS Standby Current (mA)  
Com’l/Ind’l  
Com’l  
L
3.0  
3.0  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
June 15, 2000  

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