78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
FEBRUARY 2004
DESCRIPTION
FEATURES
The 78P2344JAT is
a
low-power, 4-port
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Transmit and receive interfaces for E3, DS3 and
STS-1 applications
DS3/E3/STS1 Line Interface Unit (LIU) with
integrated Jitter Attenuator (JAT). It includes all the
required clock recovery and transmitter pulse
shaping functions for applications using 75-ohm
coaxial cable at distances up to 1350 feet. These
applications include DSLAMs, T1,3/E1,3 digital
multiplexers, SONET Add/Drop multiplexers, PDH
equipment, DS3 to Fiber optic and microwave
modems and ATM WAN access for routers and
switches.
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Designed for use with 75 ohm coaxial cable
lengths up to 1350 ft
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Receives DS3-high and DSX3 monitor signals
Local and Remote loopbacks
Selectable B3ZS/HDB3 ENDEC with line code
violation detector
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Standards-based LOS detector
Optional serial-port based mode selection and
channel status monitoring
The receiver recovers clock and data from a B3ZS
or HDB3 coded AMI signal. It can compensate for
over 12dB of cable and 6dB of flat loss. The
transmitter generates a signal that meets the
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Adaptive digital clock recovery (uses line-rate
reference clock input)
Receive output clock maintains nominal line-rate
frequency at all times
standard pulse shape requirements.
The
Fully integrated Jitter Attenuation function
provided for all line rates (no external VCXO
required)
78P2344JAT includes optional B3ZS/HDB3 ENDEC
with a receive line code violation detector, loop-back
modes, Loss of Signal detector, clock polarity
selection, and the ability to receive a DSX3 monitor
signal.
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Jitter Attenuator configurable for transmit or
receive path
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Transmit line fault monitor
Requires no external current-setting resistor or
loop filter components
STANDARDS
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Telcordia GR-499-CORE and GR-253-CORE
ITU-T G.823, G.824, G.775, and G.703
ETSI TBR-24, ETS 300 686, ETS 300 687, and
ETS EN 300 689
ANSI T1.102-1993, T1.231-1997, T1.404-1994,
and T1.105.03b
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Single 3.3V supply operation
Available in 100-pin Exposed Pad JEDEC LQFP
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BLOCK DIAGRAM
Controls Flags
RLBK
LBO E3 DS3
Transmit
TXNW
TXEN
Monitor
TPOS
TNEG
TCLK
B3ZS /
HDB3
LOUTP
LOUTN
Pulse
Shaper
Encoder
Attenuator
Jitter
Attenuator
ENDEC
RPOS
LINP
LINN
B3ZS /
AGC
Data
Detector
Adaptive
Equalizer
HDB3
RNEG
RCLK
Decoder
MON
TCLKP
RCLKP
Power
Distribution
Signal
Detector
Clock
Recovery
LOS
LLBKA
LLBKB
PDTX PDRX
CKREF
Signals from
Adjacent Port
Each Channel
CS
SCK
SDI
Master
Control
Registers
Bias
CKREF
Generator
SDO
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