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78P2343-IEL PDF预览

78P2343-IEL

更新时间: 2024-02-13 23:55:39
品牌 Logo 应用领域
东电化 - TDK PC电信电信集成电路
页数 文件大小 规格书
36页 368K
描述
PCM Transceiver, 1-Func, PQFP100, LQFP-100

78P2343-IEL 技术参数

生命周期:Active零件包装代码:QFP
包装说明:HLFQFP,针数:100
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.57Is Samacsys:N
JESD-30 代码:S-PQFP-G100长度:14 mm
功能数量:1端子数量:100
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HLFQFP
封装形状:SQUARE封装形式:FLATPACK, HEAT SINK/SLUG, LOW PROFILE, FINE PITCH
认证状态:Not Qualified座面最大高度:1.6 mm
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:PCM TRANSCEIVER温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:14 mm
Base Number Matches:1

78P2343-IEL 数据手册

 浏览型号78P2343-IEL的Datasheet PDF文件第5页浏览型号78P2343-IEL的Datasheet PDF文件第6页浏览型号78P2343-IEL的Datasheet PDF文件第7页浏览型号78P2343-IEL的Datasheet PDF文件第9页浏览型号78P2343-IEL的Datasheet PDF文件第10页浏览型号78P2343-IEL的Datasheet PDF文件第11页 
78P2343JAT  
3-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
REGISTER DESCRIPTION (continued)  
LEGEND  
TYPE DESCRIPTION  
TYPE DESCRIPTION  
R/W Read or Write  
R/O  
Read only  
GLOBAL REGISTERS  
ADDRESS 0-0: MASTER CONTROL REGISTER  
DFLT  
BIT  
NAME  
TYPE  
DESCRIPTION  
VALUE  
Register Control Enable:  
0 : Pin selection overrides register settings  
1 : Device is controlled via register set.  
7
REGEN  
R/W  
0
NOTE: Pin 15 (ENDEC) must be tied low when REGEN is enabled.  
Line Speed Selection: Selects the line speed of all channels as well as  
the input clock frequency at the CKREF pin.  
[DS3 E3] = 00 : STS-1 (51.840MHz)  
01 : E3 (34.368MHz)  
6
5
DS3  
E3  
R/W  
R/W  
X
X
10 : DS3 (44.736MHz)  
11 : STS-1 (51.840MHz)  
NOTE: The default values of these register bits depend on the state of  
the MSL0 pin upon power-up or reset.  
Encoder/Decoder Disable:  
0 : selects NRZ digital data interface  
1 : selects AMI digital data interface  
4
ENDEC  
R/W  
0
NOTE: Relevant only when the REGEN bit is set. Otherwise, ENDEC pin  
selection prevails.  
RCLK Polarity Selection:  
3
2
RCLKP  
TCLKP  
R/W  
R/W  
0
0
0 : Receive Data clocked out on the falling-edge of RCLK  
1 : Receive Data clocked out on the rising-edge of RCLK  
TCLK Polarity Selection:  
0 : Transmit Data clocked in on the rising-edge of TCLK  
1 : Transmit Data clocked in on the falling-edge of TCLK  
1
0
RSVD  
SRST  
R/O  
R/W  
X
0
Reserved  
Register Soft-Reset: When this bit is set, all registers are reset to their  
default values. Also resets Jitter Attenuator to “centered” states. This  
register bit is self-clearing.  
- 8 -  

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