Datasheet > 768143103JPSP

768143103JPSP

更新时间： 2024-11-15 04:48:11

品牌	Logo	应用领域
西迪斯 - CTS		/
页数	文件大小	规格书
5页	148K
描述
Leaded Surface Mount

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中文翻译

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768143103JPSP 数据手册

Leaded Surface Mount Series 768

TechnicalData

Features

• Medium Body Design

• Low Profile---Board to Network Clearance of

0.0075”±0.0025”

• Solid Ceramic Construction

• No Internal Dendrite Growth

• Conforms to EIA PDP-100 SOGN-0002

• Packaged in Tape & Reel or Slide Packs

• Application Specific Circuits Are Available

• Compatible With Reflow Solder Process

• RoHS Compliant

Resistance Tolerance:

Standard: ±2% or 0.5Ω (whichever is greater)

Resistance Range:

Standard: 10Ω to 1 MegΩ

Special: ±0.25% or 0.3Ω (whichever is greater)

Operating Temperature Range:

Dielectric Strength:

-55°C to +125°C

100 VAC

Temperature Coefficient:

Standard: 100Ω to 1 MegΩ

100PPM/°C typical

Maximum Operating Voltage:

50V not to exceed rated power

10Ω to 99Ω

±200PPM/°C typical

Power Rating (Total Network Power):

14 Pin

2.0w

1.3w

16 Pin

2.3w

1.5w

20 Pin

3.0w

2.0w

@25°C

@70°C

Maximum Resistor Power:

(Not to Exceed Total Network Power)

Schematic

@25°C

@70°C

0.15w

0.10w

0.30w

0.20w

0.15w

0.10w

0.15w

0.10w

1 of 5

January 2008

CTS Electronic Components

Leaded Surface Mount Series 768

www.ctscorp.com

12 3 4 5

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