Datasheet > 74VHCV574FT

74VHCV574FT

更新时间： 2023-12-06 20:13:19

品牌	Logo	应用领域
东芝 - TOSHIBA		/
页数	文件大小	规格书
13页	189K
描述
Octal D-Type Flip-Flop, TSSOP20B

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74VHCV574FT 数据手册

74VHCV574FT

11.7. AC Characteristics (Unless otherwise specified, Ta = 25 , Input: tr = tf = 3 ns)

Test

Condition

Characteristics

Symbol

Note

VCC (V)

CL (pF)

Min

Typ.

Max

Unit

Propagation delay time

(CK-Q)

tPLH,tPHL



2.5 ± 0.2



130



9.1

11.9

6.7

8.9

5.0

6.7

7.6

10.7

5.7

8.1

4.2

6.1

13.6

10.5

8.2

16.6

19.6

13.2

16.7

8.6

3.3 ± 0.3

5.0 ± 0.5

2.5 ± 0.2

3.3 ± 0.3

5.0 ± 0.5

10.6

16.1

19.0

12.8

16.3

9.0

3-state output enable time

tPZL,tPZH

RL = 1 kΩ

11.0

17.5

15.0

10.1



3-state output disable time

Maximum clock frequency

tPLZ,tPHZ

fMAX

RL = 1 kΩ

2.5 ± 0.2

3.3 ± 0.3

5.0 ± 0.5

2.5 ± 0.2



MHz



3.3 ± 0.3

5.0 ± 0.5

135

100

180

135



Output skew

tosLH,tosHL (Note 1)



2.5 ± 0.2

3.3 ± 0.3

5.0 ± 0.5

2.0



1.5



1.0

Input capacitance

CIN



Output capacitance

COUT



Power dissipation capacitance

CPD

(Note 2)



Note 1: Parameter guaranteed by design. (tosLH = |tPLHm-tPLHn|, tosHL = |tPHLm-tPHLn|)

Note 2: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current

consumption without load. Average operating current can be obtained by the equation.

ICC(opr) = CPD × VCC × fIN + ICC/8 (per latch)

And the total CPD when n pcs. of latch operate can be gained by the following equation.

CPD (total) = 14 + 12 × n

2016-08-05

Rev.2.0

1...6 7 8910 11 12 13

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