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74VMEH22501ADGGRG4 PDF预览

74VMEH22501ADGGRG4

更新时间： 2024-01-15 18:00:15
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
31页 935K
描述
74V SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO48, GREEN, PLASTIC, TSSOP-48

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74VMEH22501ADGGRG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP48,.3,20针数：48
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.37其他特性：TWO 1-BIT TRANSCEIVERS ALSO AVAILABLE
控制类型：COMMON CONTROL计数方向：BIDIRECTIONAL
系列：74VJESD-30 代码：R-PDSO-G48
JESD-609代码：e4长度：12.5 mm
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER最大I（ol）：0.012 A
湿度敏感等级：1位数：8
功能数量：1端口数量：2
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE WITH SERIES RESISTOR
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP48,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：260
电源：3.3 V最大电源电流（ICC）：30 mA
Prop。Delay @ Nom-Sup：14.5 ns传播延迟（tpd）：10.1 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.45 V
最小供电电压 (Vsup)：3.15 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：6.1 mm
Base Number Matches：1

74VMEH22501ADGGRG4 数据手册

 浏览型号74VMEH22501ADGGRG4的Datasheet PDF文件第2页浏览型号74VMEH22501ADGGRG4的Datasheet PDF文件第3页浏览型号74VMEH22501ADGGRG4的Datasheet PDF文件第4页浏览型号74VMEH22501ADGGRG4的Datasheet PDF文件第5页浏览型号74VMEH22501ADGGRG4的Datasheet PDF文件第6页浏览型号74VMEH22501ADGGRG4的Datasheet PDF文件第7页 
SN74VMEH22501A  
www.ti.com  
SCES3620A –DECEMBER 2004–REVISED FEBRUARY 2010  
8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS  
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS  
Check for Samples: SN74VMEH22501A  
1
FEATURES  
•
Member of the Texas Instruments Widebus™  
Family  
•
ESD Protection Exceeds JESD 22  
–
–
–
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
•
UBT™ Transceiver Combines D-Type Latches  
and D-Type Flip-Flops for Operation in  
Transparent, Latched, or Clocked Modes  
1000-V Charged-Device Model (C101)  
DGG OR DGV PACKAGE  
(TOP VIEW)  
•
•
•
OEC™ Circuitry Improves Signal Integrity and  
Reduces Electromagnetic Interference (EMI)  
Compliant With VME64, 2eVME, and 2eSST  
Protocols  
Bus Transceiver Split LVTTL Port Provides a  
Feedback Path for Control and Diagnostics  
Monitoring  
•
•
•
•
I/O Interfaces Are 5-V Tolerant  
B-Port Outputs (–48 mA/64 mA)  
Y and A-Port Outputs (–12 mA/12 mA)  
Ioff, Power-Up 3-State, and BIAS VCC Support  
Live Insertion  
•
•
Bus Hold on 3A-Port Data Inputs  
26-Ω Equivalent Series Resistor on 3A Ports  
and Y Outputs  
•
•
•
Flow-Through Architecture Facilitates Printed  
Circuit Board Layout  
Distributed VCC and GND Pins Minimize  
High-Speed Switching Noise  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
DESCRIPTION/ORDERING INFORMATION  
The SN74VMEH22501A 8-bit universal bus transceiver has two integral 1-bit three-wire bus transceivers and is  
designed for 3.3-V VCC operation with 5-V tolerant inputs. The UBT™ transceiver allows transparent, latched, and  
flip-flop modes of data transfer, and the separate LVTTL input and outputs on the bus transceivers provide a  
feedback path for control and diagnostics monitoring. This device provides a high-speed interface between cards  
operating at LVTTL logic levels and VME64, VME64x, or VME320(1) backplane topologies.  
The SN74VMEH22501A is pin-for-pin capatible to the SN74VMEH22501 (TI literature number SCES357), but  
operates at a wider operating temperature (−40°C to 85°C) range.  
(1) VME320 is a patented backplane construction by Arizona Digital, Inc.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2004–2010, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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